Vincent Ming Cheong Poon

Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method

High performance super TFTs with different channel widths and lengths, formed by a novel grain enhancement method, are reported. High temperature annealing has been utilized to enhance the polysilicon grain and improve the quality of silicon crystal after low temperature MILC treatment on amorphous silicon. With device scaling, it is possible to fabricate the entire transistor on a single grain, thus giving the performance of single crystal SOI MOSFET. The effects of grain boundaries on device performance have been studied, indicating the existence of extra leakage current paths caused by the grain boundaries traversing the channel, which induced subthreshold hump and early punchthrough of wide devices. The probability for the channel region of a TFT to cover multiple grains decreases significantly when the device is scaled down, resulting in better device performance and higher uniformity.

Investigation of Polycrystalline Nickel Silicide Films as a Gate Material

The work function of polycrystalline nickel silicide film formed by rapid thermal annealing (RTA) has been studied using capacitance-voltage (C-V) measurements and metal-oxide semiconductor (MOS) structures. The effect of sintering temperature on work function has also been studied. Results show that the work function of n + -doped NiSi gate is about 4.6 eV and is stable from 400 to 800°C. For p + -doped NiSi gate, the work function is 5 eV. The gate-substrate leakage current is small and the oxide quality is similar to that in Al-gate MOS capacitors even for oxides as thin as 8 nm. The poly-gate depletion effect (PDE) has also been investigated by quasi-static C-V. Compared with that of poly-Si and poly-Si 1-x Ge x , no PDE is observed in silicide-gate n-MOS device even when the gate is undoped. The results suggest that nickel silicide film may be used as a potential gate material in complementary MOS or thin-film transistor devices.

Interface structure of ultrathin oxide prepared by N/sub 2/O oxidation

With X-ray photoelectron spectroscopy (XPS) measurements, we found in the N/sub 2/O-grown oxide that the nitrogen incorporation should involve the NO or N reaction with the Si-Si bond and P/sub b/ centers at the interface. Consequently, nitrogen content is very low and accumulated mainly at the interface. In addition, we found that the nitrogen atoms at the interface exist in the form of Si-N bonding and the interface oxynitride layer is a mixture of SiO/sub 2/ and Si/sub 3/N/sub 4/ clusters. This structure will result in several undesirable effects. It will give rise to the permittivity and bandgap fluctuations at the interface and hence induced gigantic surface potential fluctuation and mobility degradation in the channel of MOS devices. This bonding structure also explains the interface trap generation during the electrical stressing. The sources of trap generation are attributed to the Si-Si bonds, P/sub b/ centers, and nitride-related defects due to the over-constrained silicon atoms in the Si/sub 3/N/sub 4/ clusters at the interface.

Modeling of grain growth mechanism by nickel silicide reactive grain boundary effect in metal-induced-lateral-crystallization

The growth mechanism of metal-induced-lateral-crystallization (MILC) was studied and modeled. Based on the time evolution of the metal impurity in the amorphous silicon film being crystallized, a model has been developed to predict the growth rate and the final metal distribution in the crystallized polysilicon. The model prediction has been compared with experimental results and high prediction accuracy is demonstrated. Using the model, the effects of annealing temperature, annealing time and initial metal concentration on the final grain size and metal impurity distribution can be analyzed. As a result, the model can be used to optimize the grain growth conditions for fabricating high performance thin-film-transistors on the recrystallized polysilicon film.

Characterization of MOSFETs fabricated on large-grain polysilicon on insulator

Abstract Large-grain polysilicon on insulator films, formed by utilizing metal induced unilateral crystallization (MIUC) of amorphous silicon film and subsequent high temperature annealing, has been used to fabricate high performance MOSFETs. The corelation between the improvement of device characteristics and of grain size enhancement has been studied. It was found that the MOSFET characteristics have a strong dependence on both device width and length. Substantially better characteristics of devices fabricated on the enhanced films compared with other recrystallization methods are observed in large devices. Significant improvement in device characteristics has been demonstrated as the dimension is reduced. The statistical variation on device parameters has also been studied and the most significant device-to-device variation is found when the transistor size is around the size of the silicon grains.

A Conductivity Modulated Polysilicon Thin-Film Transistor

This paper reports a novel high voltage Conductivity Modulated Thin-Film Transistor (CMTFT) fabricated using polycrystalline silicon. The transistor uses the idea of conductivity modulation in the offset region to obtain a significant reduction in on-state resistance. Experimental on-state and off-state current-voltage characteristics of the CMTFT have been compared with those of the conventional offset drain device. Results show that the CMTFT has six times to more than three orders of magnitude higher on-state current handling capability for operating at drain voltages ranging from 15 V to 5 V while still maintaining low leakage current and providing even faster switching speed. The CMTFT devices can be fabricated using a low temperature process (620/spl deg/C) which is highly desirable for large area electronic applications.<<ETX>>

Implemention of linear doping profiles for high voltage thin-film SOI devices

In this paper, a novel approach is proposed to obtain a linear doping profile for the implementation of lateral high voltage devices on thin-film Silicon-On-Insulator (SOI). The linear doping profile is obtained by using a lateral variation doping technique. In this technique, a smeared-out dopant distribution is implemented through the use of a sequence of small opening slits in the oxide mask with subsequent impurity implantation and drive-in processes. To understand the effect of the location and size of the oxide slits on the final doping profile, an one-dimensional analytical model is developed. Moreover, a computer program has also been developed to facilitate the slit parameters optimization. Validity of the model and the program has been verified by performing extensive two-dimensional process and device simulations.

Electrostatic analysis of field emission triode with volcano‐type gate

More researchers have recently paid much attention to the fabrication of field emission triode with a volcano‐type gate on the silicon substrate because of their ease of fabrication and low cost. In this article, five different structures of this triode are presented. The electric field on the tip of field emitter (Etip) is calculated for these structures by using the EMAS software, and the different potential distribution and electric field distribution are obtained from these calculations. The results show that the diameter of the gate hole is important in determining Etip for this triode. Because the volcano‐type gate holes fabricated by wet or dry etching have a very sharp rim, when the distance between anode and gate is small, a high electric field more than 1×107 V/cm is formed on the rim of gate hole at the given gate voltage Vg and anode voltage Va.

A fast switching insulated-gate P-I-N diode controlled thyristor structure

A new Insulated-Gate PIN Diode Controlled Thyristor (IGPDT) structure is reported. Its on-state and turn-off characteristics are studied using two-dimensional numerical simulations. Results show that the IGPDT achieves similar on-state characteristics compared to that of the trench BRT (Base Resistance Controlled Thyristor), and also provides gate turn-off capability up to current density of several hundred A/cm/sup 2/. However, resistive switching turn-off speed of the IGFDT is approximately 3 times faster than that of the trench BRT.

A novel emitter-sharpened double-gate race-track-shaped field emitter structure

In this paper, a new emitter-sharpened double-gate race-track-shaped field emitter structure is reported. The race-track-shaped edge emission with double-gate control is used to provide high uniformity FEAs over a large area without the need of expensive submicron technology. In order to minimize the gate current, which is detrimental to the field emitter performance, an emitter-sharpened structure is used. Experimental results show that the turn-on voltage of the emitter-sharpened double-gate structure is 45 V, which is 60% smaller than that of the single-gate structure (110 V). Furthermore, the gate current of the emitter-sharpened double-gate structure is 7 times and 15 times smaller than that of the nonemitter-sharpened double-gate structure and the single-gate structure, respectively.