Vipin Tiwari

A 55 nm Logic-Process-Compatible, Split-Gate Flash Memory Array Fully Demonstrated at Automotive Temperature with High Access Speed and Reliability

In this paper, a Flash macro designed with high-density arrays of split-gate (SG) SuperFlash® cells, compatibly embedded in a 55 nm Low Power (LP) logic process is demonstrated with full functionality and excellent reliability at automotive temperature range. This split-gate Flash memory technology can be seamlessly and universally embedded in multiple logic process platforms, and can continually be scaled to 40 nm and smaller lithographically nodes, without compromising performance and reliability.

Split-Gate Floating Poly SuperFlash ® Memory Technology, Design, and Reliability

Split-gate embedded flash memory technology has been around for a couple of decades and has become a de facto standard for embedded products such as microcontrollers and smart cards. The majority of the large microcontroller and smartcard chip-makers and a series of fabless companies are now using some form of a split-gate embedded flash-memory technology because of its advantages in power, performance, and cost compared with traditional EEPROM or stacked-gate solutions. This chapter covers the fundamentals of split-gate embedded flash memories with an emphasis on SST’s widely adopted SuperFlash® memory technology as an example to demonstrate the benefits of a split-gate embedded flash-memory technologies. The fundamentals of SuperFlash technology, design, reliability, and scalability are discussed in detail in various sections, which would provide a detailed understanding of a split-gate, embedded flash-memory technology.

40nm Embedded Self-Aligned Split-Gate Flash Technology for High-Density Automotive Microcontrollers

This paper successfully demonstrates a logic- compatible, high performance and high reliability, automotive-grade 2.5V embedded NVM process extending over several generations. A high-density flash macro is used to debug process complexities which arise from the add-on modules. The modular approach is adopted for integrating self-aligned, floating-gate-based split-gate SuperFlash® ESF3 cell into 40nm CMOS logic process. Key features of the product-like Macro are dual power supply with input voltage fluctuations, wide operating temperature range from -40ºC to 150ºC, fast byte/word program under 10s and sector/chip erase under 10ms. The macro random read access time is only 8ns under worst case conditions. Key process monitors are characterization and yield of the Macro. Endurance was extended to 200k cycles and satisfy automotive grade requirement with wide read margin. Post-cycling data retention performs very well up to 150ºC. Wafer sort yield is in high double digits, with consistent wafer-to-wafer and within-wafer uniformity, showing good process control. The technology is suitable for high-speed automotive MCU, as well as IoT, smart card, and industrial MCU applications.