Vito Giannini

How much energy is needed to run a wireless network

In order to quantify the energy efficiency of a wireless network, the power consumption of the entire system needs to be captured. In this article, the necessary extensions with respect to existing performance evaluation frameworks are discussed. The most important addenda of the proposed energy efficiency evaluation framework (E3F) are a sophisticated power model for various base station types, as well as large-scale long-term traffic models. The BS power model maps the RF output power radiated at the antenna elements to the total supply power of a BS site. The proposed traffic model emulates the spatial distribution of the traffic demands over large geographical regions, including urban and rural areas, as well as temporal variations between peak and off-peak hours. Finally, the E3F is applied to quantify the energy efficiency of the downlink of a 3GPP LTE radio access network.

Cellular Energy Efficiency Evaluation Framework

In order to quantify the energy savings in wireless networks, the power consumption of the entire system needs to be captured and an appropriate energy efficiency evaluation framework must be defined. In this paper, the necessary enhancements over existing performance evaluation frameworks are discussed, such that the energy efficiency of the entire network comprising component, node and network level contributions can be quantified. The most important addendums over existing frameworks include a sophisticated power model for various base station (BS) types, which maps the RF output power radiated at the antenna elements to the total supply power of a BS site. We also consider an approach to quantify the energy efficiency of large geographical areas by using the existing small scale deployment models along with long term traffic models. Finally, the proposed evaluation framework is applied to quantify the energy efficiency of the downlink of a 3GPP LTE radio access network.

An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS

Current trends in analog/mixed-signal design for battery-powered devices demand the adoption of cheap and power-efficient ADCs. SAR architectures have been recently demonstrated as able to achieve high power efficiency in the moderate-resolution/medium- bandwidth range in Craninckx, J. and Van der Plas, G., (2007). However, when the comparator determines in first instance the overall performance, as in most SAR ADCs, comparator thermal noise can limit the maximum achievable resolution. More than 1 and 2 ENOB reductions are observed in Craninckx, J. and Van der Plas, G., (2007) and Kuttner, F., (2002), respectively, because of thermal noise, and degradations could be even worse with scaled supply voltages and the extensive use of dynamic regenerative latches without pre-amplification. Unlike mismatch, random noise cannot be compensated by calibration and would finally demand a quadratic increase in power consumption unless alternative circuit techniques are devised.

A 4th-order active-G/sub m/-RC reconfigurable (UMTS/WLAN) filter

A fourth-order low-pass continuous-time filter for a UMTS/WLAN receiver of a reconfigurable terminal is presented. The filter uses the cascade of two Active-Gm-RC biquad cells. A single opamp is used for each biquad and its unity-gain-bandwidth is comparable to the filter cut-off frequency. Thus, the opamp power consumption is strongly reduced w.r.t. other closed-loop filter configurations. The cut-off frequency deviation due to the technological spread, aging and temperature variation is adjusted by an on-chip tuning circuit. The device in a 0.13 mum CMOS technology occupies a 0.9 mm2 area and it consumes 3.4 mW and 11 4.2 mW for the UMTS and WLAN, respectively. The full chip has been designed using an automatic design tool, which is validated by the agreement between the experimental results and the expected performance

Flexible Baseband Analog Circuits for Software-Defined Radio Front-Ends

This paper presents a novel approach to design a digitally programmable low pass filter (LPF) and variable gain amplifier (VGA) intended for a software-defined radio (SDR) front-end. These flexible analog circuits are driven by a network-on-chip (NoC) that is able to set performance parameters like cut-off frequency, selectivity, noise, and gain guaranteeing at any time a near-optimal power/performance trade-off. A design approach is proposed to tackle the challenges imposed by flexibility in analog design. A silicon prototype is realized in 0.13-mum CMOS technology with 1.2-V supply voltage to prove the validity of the proposed solution. The LPF provides a frequency tuning range between 0.35 MHz and 23.5 MHz with an adaptive integrated noise level between 85 muVrms and 163 muVrms whereby the power consumption conveniently varies from 0.72 mW to 21.6 mW according to the required performance. The VGA is made up of two cascaded gain stages and provides a gain range from about 0 dB to 39 dB with a reconfigurable power/bandwidth.

A 40 nm CMOS 0.4–6 GHz Receiver Resilient to Out-of-Band Blockers

A highly-linear software-defined radio operating from 400 MHz to 6 GHz is presented, with the purpose of removing any dedicated filtering at the antenna. Very high resilience to out-of-band interference is achieved thanks to a 2.5 V linear LNA and mixer-based RF blocker filter. The 2 mm2, 40 nm digital CMOS receiver achieves +10 dBm out-of-band IIP3 and >; +70 dBm calibrated IIP2 at 3 dB NF. It tolerates 0 dBm blockers at 20 MHz offset with acceptable blocker NF.

A 2-mm

A software-defined radio (SDR) should theoretically receive any modulated frequency channel in the (un)licensed spectrum, and guarantee top performance with energy savings, while still being integrated in a digital CMOS technology. This paper demonstrates a practical 0.1-5 GHz front-end implementation for such an SDR concept, including receiver and local oscillator (LO), with only 2-mm2 core area occupation in a 45-nm CMOS process. This scalable radio uses shunt-shunt feedback LNAs, a passive mixer with enhanced out-of-band IIP3, and a fifth order low-area 0.5-20 MHz baseband filter. LO quadrature signals are generated from a dual-VCO 4-10 GHz fractional-N PLL. With noise figure between 2.3 dB and 6.5 dB, out-of-band IIP3 between -3 dBm and -10 dBm, and total power consumption between 59 and 115 mW from a 1.1-V supply voltage, the presented prototype favorably compares with state-of-the-art dedicated radios while enabling, for the first time, wideband reconfigurable performance and energy scalability.

^{2}

A 5 mm2 transceiver front-end suitable for a software-defined radio (SDR) platform is implemented in a 40-nm LP digital CMOS technology. Tailored for all modern communication standards relevant for a modern handheld mobile device (2G/3G/4G cellular, WLAN, Bluetooth, GPS, broadcasting, etc.), it uses radio architectures and circuits that ensure flexible performance at a minimal cost in area and power consumption. The receive section features four parallel LNAs to cover the frequency range from 100 MHz up to 6 GHz, a 25 % duty cycle passive mixer with IIP2 calibration, fifth-order baseband filtering up to 20 MHz, variable-gain amplification, and a 10-b 65 MS/s 34 fj/conv-step SAR ADC. It achieves NF down to 2.4 dB, more than 30-dB EVM and 50-dBm IIP2. In the transmit section, main emphasis is given to the out-of-band noise requirement that enables SAW-less operation in FDD systems: a flexible reconstruction filter is followed by a voltage-sampling mixer and a variable gain PPA. The TX chain achieves 3.2% EVM at 0-dBm output power, with CNR down to-156 dBc/Hz. For frequency synthesis, two dual-VCO 5.9-12.8 GHz fractional-N PLLs are implemented together with a chain of divide-by-2 circuits for quadrature generation.

0.1–5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS

A 86 MHz-12 GHz digital-intensive reconfigurable PLL frequency synthesizer is presented with 100 kHz to 2 MHz bandwidth. It leverages a 6 fJ/step 5.5 ps, 14b coarse-fine TDC and a 6-12 GHz dual-VCO set. Several simple calibration schemes are proposed that enable the proper performance of the highly efficient TDC in the PLL. The 0.28 mm2 synthesizer, which is appropriate for use in a Software-Defined Radio, features noise cancellation and digital phase modulation and consumes less than 30 mW.

A 5 mm

A fully reconfigurable SDR contains an RX, a TX, and 2 synthesizers for true multi-standard operation. A MEMS-enabled dual-band LNA proves the feasibility of switched antenna filtering for interference robustness. The baseband section is programmable in noise level and in bandwidth from 350kHz to 23MHz. The receiver has 6dB NF, -9dBm IIP3, and up to 90dB gain. Implemented in a 0.13μmum CMOS process, it draws 62mA to 120mA in RX mode and 56mA to 89mA in TX mode from a 1.2V supply.