C. Soens

Low-Area Active-Feedback Low-Noise Amplifier Design in Scaled Digital CMOS

The emerging concept of multistandard radios calls for low-noise amplifier (LNA) solutions able to comply with their needs. Meanwhile, the increasing cost of scaled CMOS pushes towards low-area solutions in standard, digital CMOS. Feedback LNAs are able to meet both demands. This paper is devoted to the design of low-area active-feedback LNAs. We discuss the design of wideband, narrowband and multiband implementations. We demonstrate that competitive RF performance is achievable thanks to CMOS downscaling, pleasing many applications because of their low cost (digital CMOS) and low area (bondpad size).

A 2-mm

A software-defined radio (SDR) should theoretically receive any modulated frequency channel in the (un)licensed spectrum, and guarantee top performance with energy savings, while still being integrated in a digital CMOS technology. This paper demonstrates a practical 0.1-5 GHz front-end implementation for such an SDR concept, including receiver and local oscillator (LO), with only 2-mm2 core area occupation in a 45-nm CMOS process. This scalable radio uses shunt-shunt feedback LNAs, a passive mixer with enhanced out-of-band IIP3, and a fifth order low-area 0.5-20 MHz baseband filter. LO quadrature signals are generated from a dual-VCO 4-10 GHz fractional-N PLL. With noise figure between 2.3 dB and 6.5 dB, out-of-band IIP3 between -3 dBm and -10 dBm, and total power consumption between 59 and 115 mW from a 1.1-V supply voltage, the presented prototype favorably compares with state-of-the-art dedicated radios while enabling, for the first time, wideband reconfigurable performance and energy scalability.

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A fully reconfigurable SDR contains an RX, a TX, and 2 synthesizers for true multi-standard operation. A MEMS-enabled dual-band LNA proves the feasibility of switched antenna filtering for interference robustness. The baseband section is programmable in noise level and in bandwidth from 350kHz to 23MHz. The receiver has 6dB NF, -9dBm IIP3, and up to 90dB gain. Implemented in a 0.13μmum CMOS process, it draws 62mA to 120mA in RX mode and 56mA to 89mA in TX mode from a 1.2V supply.

0.1–5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS

The link budget of multi-Gb/s wireless communication systems around 60GHz improves by beamforming. CMOS realizations for this type of communication are mostly limited to either one-antenna systems [1], or beamforming ICs that do not implement all radio functions [2]. The sliding-IF architecture of [3] uses RF phase shifting, which deteriorates noise performance.

A Fully Reconfigurable Software-Defined Radio Transceiver in 0.13μm CMOS

In mixed analog-digital designs, digital switching noise is an important limitation for the performance of analog and RF circuits. This paper reports a physical model describing the impact of digital switching noise on LC-tank voltage-controlled oscillators (VCOs) in lightly doped substrates. The model takes into account the propagation from the source of substrate noise to the different components in the VCO and the resulting modulation of the oscillator frequency. The model is validated with measurements on a 3.5-GHz LC-tank VCO designed in 0.18-/spl mu/m CMOS. It reveals that for this VCO, impact occurs mainly via the nonideal metal ground lines for lower frequencies and low tuning voltage and via the integrated inductors for higher frequencies and high tuning voltage. To make the design immune to substrate noise, the parasitic resistance of the on-chip ground interconnect has to be kept as low as possible and inductors have to be shielded. Hence, the developed model allows investigating the dominant mechanisms behind the impact of substrate noise on a VCO, which is crucial information for achieving a substrate noise immune design.

A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication

A Software-Defined Radio (SDR) analog front-end is presented that provides extensive programmability of LO generator, LNA, mixers, baseband filters and PPA, supporting various wireless communication standards while guaranteeing a near-optimal power/performance trade-off at any time. The circuit is integrated in a 0.13 mum CMOS technology with 1.2 V supply voltage. This transceiver covers the frequency range from 100 MHz up to 6 GHz by exploiting a flexible zero-IF architecture. The receive path achieves a Noise Figure of 4.8 dB at 174 MHz and 6 dB at 2.4 GHz. For a WLAN OFDM 64 QAM output, the transmitter achieves an EVM better than -29 dB for -0.5 dBm output power at 2.4 GHz and -3.1 dBm output power at 4.9 GHz.

Performance degradation of LC-tank VCOs by impact of digital switching noise in lightly doped substrates

The requirements of next-generation wireless terminals are driving RFIC design toward ubiquitous multistandard connectivity at reduced power consumption and cost [1–3]. While the use of scaled CMOS technology is required to allow economically feasible single-chip integration with a digital processor, a Software-Defined Radio (SDR) is the preferred approach to provide a reconfigurable platform, that covers a broad range of noise/linearity specifications while offering the best power/performance trade-off [4,5].

A CMOS 100 MHz to 6 GHz software defined radio analog front-end with integrated pre-power amplifier

Coupling of digital switching noise to the silicon substrate can severely degrade the analog and RF performance in single-chip transceivers. To predict the degradation of the performance of RF circuits, modeling of the impact of substrate noise is absolutely necessary. Using measurements, this impact is modeled by the cascade of an attenuation through the substrate from the source of substrate noise to the RF circuit and the propagation through the RF circuit to its output. This approach has been validated with measurements on a 0.25 /spl mu/m CMOS low-noise amplifier (LNA) and reveals insight in the mechanism of impact of substrate noise on RF circuits. In addition, impact of a real digital circuit is measured on a 0.18 /spl mu/m differential CMOS LNA.

A 2mm 2 0.1-to-5GHz SDR receiver in 45nm digital CMOS

This paper proposes a compact antenna package in low-temperature co-fired ceramic (LTCC) technology for 60 GHz wireless transmission of uncompressed video. A 60 GHz active phased-array antenna is realized in the package by integrating 4 open-waveguide antenna elements at the top of the package with a 60 GHz CMOS chip at the bottom of the package. The LTCC build-up was designed to provide low interconnection loss between antenna elements and chip (insertion loss<1 dB), good antenna performance in the full unlicensed 60 GHz band (gain>5.3 dBi) and excellent shielding of the bottom side of the package containing the CMOS chip from the radiation emerging from the top side of the package (>40dB suppression). The low backside radiation allows the direct ball-grid array assembly of the package on a printed circuit-board. Only passive antenna arrays and interconnect lines were fabricated and tested in this paper. Separate transmitter (Tx) and receiver (Rx) modules were also designed in this package. Both modules have a size of only 9.5 × 9.5 × 0.8 mm3. The flip-chip assembly of the CMOS chip on the package is still under fabrication.

RF performance degradation due to coupling of digital switching noise in lightly doped substrates

Analog and RF circuit performance in single-chip transceivers can severely suffer from coupling of digital switching noise to the silicon substrate. To predict this performance degradation, a deeper understanding of the impact of substrate noise is absolutely necessary. Using measurements, this impact is studied as the cascade of attenuation through the substrate from the source of substrate noise to the RF circuit and the propagation through the RF circuit to its output. This approach has been validated with measurements on a 0.25 /spl mu/m and a 0.18 /spl mu/m CMOS low-noise amplifier (LNA) and reveals insight in the mechanisms of impact of substrate noise on RF circuits. In addition, impact of a real digital circuit is measured on a 0.18 /spl mu/m differential CMOS LNA.