Vittorio Colonna

A low-power 98-dB multibit audio DAC in a standard 3.3-V 0.35-/spl mu/m CMOS technology

An oversampled digital-to-analog converter (DAC) is presented. The performance of this device has been achieved with a careful tradeoff with power consumption. A digital /spl Sigma//spl Delta/ modulator has been optimized for the 96-dB target. In the switched-capacitor reconstruction filter (SCF), the input structure is embedded in the feedback loop in order to reduce the output noise. The order of the SCF is three, larger than in competitive solutions, allowing to achieve a lower out-of-band noise. Finally, the differential-to-single-ended converter does not strongly limit the overall DAC channel performance. The device has been realized in a standard 3.3-V CMOS technology. With a 28-mW-per-channel power consumption the dynamic range is 98 dB, while the SNDR peak is 86 dB.

A 0.22-mm/sup 2/ 7.25-mW per-channel audio stereo-DAC with 97-dB DR and 39-dB SNR/sub out/

In the stereo audio DAC here presented, the tradeoff between area-power consumption-SNR/sub out/-dynamic range is optimized for the case of a 96-dB audio system. Using a single-opamp switched-capacitor structure for the reconstruction filter, a hybrid FIR/IIR transfer function allows to reject out-of-band noise. This circuit solution strongly reduces area and power consumption. In a 0.13-/spl mu/m CMOS technology, the stereo DAC achieves a 97-dB dynamic range and a 39-dB SNR/sub out/ with a 0.22-mm/sup 2/ area and 7.25-mW power consumption per channel.

A 10.7-MHz self-calibrated switched-capacitor-based multibit second-order bandpass /spl Sigma//spl Delta/ modulator with on-chip switched buffer

A second-order multibit bandpass /spl Sigma//spl Delta/ modulator (BP/spl Sigma//spl Delta/M) used for the digitizing of AM/FM radio broadcasting signals at a 10.7-MHz IF is presented. The BP/spl Sigma//spl Delta/M is realized with switched-capacitor (SC) techniques and operates with a sampling frequency of 37.05 MHz. The input impulse current, required by the SC input branch, is minimized by the use of a switched buffer without deteriorating the overall system performance. The accuracy of the in-band noise shaping is ensured with two self-calibrating control systems. In a 0.18-/spl mu/m CMOS technology, the device die size is 1 mm/sup 2/ and the power consumption is 88 mW. In production, the BP/spl Sigma//spl Delta/M features at least 78-dB dynamic range and 72-dB peak SNR within a 200-kHz bandwidth (FM bandwidth). The intermodulation (IMD) is -65 dBc for two tones at -11 dBFS. The robustness of the aforementioned performance is demonstrated by the fact that it has been realized with the BP/spl Sigma//spl Delta/M embedded in the noisy on-chip environment of a complete mixed-signal FM receiver.

Self-tuning algorithms for high-performance bandpass switched-capacitor /spl Sigma//spl Delta/ modulators

Switched-capacitor high-frequency bandpass /spl Sigma//spl Delta/ modulators could suffer from capacitor mismatch, finite opamp dc gain, and finite opamp bandwidth. These problems make the notch frequency and the quality factor of the zeros of the noise transfer function to deviate from their nominal values, strongly affecting the modulator dynamic range (DR). In order to avoid this situation, two sampled-data algorithms have been developed which allow to self-calibrate the bandpass /spl Sigma//spl Delta/ modulators. They use 3500 gate and 0.043 mm/sup 2/ area and consume power only when they are active, while, when the system is on, they are off and do not interfere with standard operation. The validity of the proposal is demonstrated by a silicon prototype in which the proposed solution allows to guarantee a 75-dB DR performance also under worst case conditions. In the particular case, it allows for the recovery of 3 dB in the SNR for the 200-kHz FM band (from 73 to 76 dB).

A compact-disc analog-to-digital front-end in BiCMOS technology

A BiCMOS analog front-end to be used in a complete two-chip set with a digital signal processor for compact disc (CD) applications is presented. The proposed device exchanges data with the digital counterpart by means of a I2C-like bus serial interface. Four input signals (currents or voltages) are preamplified with flat group-delay and digitized with 6-bit (for servo path) and 6-bit (for RF path) accuracy. This accuracy is achieved without using an equalizer in the signal path. The system is designed to process CD signal with speed up to 4/spl times/ (i.e. 3.2 MHz bandwidth). The device is realized in a 0.7 /spl mu/m BiCMOS technology using 21.5 mm/sup 2/ chip area.

A CD analog front–end in BiCMOS technology

A BiCMOS analog front-end to be used in a complete two-chip set with a digital signal processor for Compact Disk (CD) is presented. The proposed device exchanges data with the digital counterpart by means of a I2C-like bus serial interface. Four input signals (current or voltage) are preamplified with flat group-delay and digitized with 6-bit (for servo path) and 8-bit (for RF path) accuracy. This accuracy is achieved without using an equalizer in the signal path. The system is designed to process CD signal with speed up to 4x (i.e. 3.2MHz bandwidth). The device is realized in a 0.7µm BiCMOS technology using 21.5mm2chip area.

A DSP-based digital IF AM/FM car-radio receiver

This paper describes the design and the implementation of a DSP-based digital IF (intermediate frequency) radio receiver in a low-power 0.18/spl mu/m CMOS technology. Thanks to an advanced systems-on-chip mixed analog and digital solution, the proposed device performs the demodulation of both AM and FM stereo signals, digitized at the IF by means of a high dynamic range /spl Sigma//spl Delta/-bandpass analog to digital converter. The chosen architecture combines hardware and software functions, yielding true blind equalization of the FM channel; this results in an outstanding rejection of the adjacent channels and of any other interfering signal, even under severe multipath conditions. The described chip occupies as small as 15.21mm/sup 2/ and it is shipped in a compact 64-pin package, reducing application costs while ensuring state-of-the-art performance.

90dB-DR 3.3V CMOS Single-Ended-to-Fully-Differential and Fully-Differential-to-Single-Ended Amplifiers for Audio Applications

This paper presents the design and the realization of single-ended-to-fully differential and fully differential-to-single-ended amplifiers to be used in an audio signal processing system. The proposed blocks allow to reduce significantly the pin number of the developed system, while guaranteeing the high quality (16bit) performance required in an audio channel. The proposed circuits have been realized in a standard 3.3V 0.35 µm CMOS technology and achieve a Dynamic Range in excess of 90dB with a Total Harmonic Distortion lower than -80dB for a full scale signal amplitude. Their power consumption (≈6mW and each) and the area (0.1mm2 each) are finally negligible with respect to the other blocks in the overall systems. Copyright

A 94dB-SNR −76dB-THD high-efficiency hybrid audio power-DAC for loudspeaker (4Ω/8Ω) and earphone (16Ω/32Ω)

This paper presents a high-efficiency audio DAC with a class-AB power output stage in the analog reconstruction filter. This closed-loop solution reduces power stage noise and linearity specs, reduces the active device number, and, definitively, reduces power consumption, increasing efficiency. Moreover, a novel control system allows, at the same time, to reduce output offset and idle tone generated by the digital structure. In a 0.15µm CMOS technology at 2.7V supply, the powerDAC performs 94dB-SNR, and −76dB-THD on 80-load. The output offset is reduced to be lower than 500µV. The efficiency FoM defined as DeliveredPower/QuiescentPower of the overall analog block is >40 (on a 16 load), while the efficiency FoM of the earphone PA stand alone is 56. In both case the proposed device efficency outperforms the state-of-the-art [6–9].

A 0.22mm/sup 2/ 7.25mW per-channel audio stereo-DAC with 97dB-DR and 39dB SNRout

In the stereo audio DAC presented here, the trade-off between area-power consumption-SNRout-dynamic range is optimized for the case of a 96 dB audio system. Using a single-op amp switched capacitor structure for the reconstruction filter, a hybrid FIR/IIR transfer function allows it to reject out-of-band noise. This circuit solution strongly reduces area and power consumption. In a 0.13 /spl mu/m CMOS technology, the stereo DAC achieves a 97 dB-dynamic range and a 39 dB SNRout with a 0.22 mm/sup 2/ area and 7.25 mW power consumption per-channel.