Thomas Steininger

Requirements and Concepts for Transaction Level Assertions

The latest development of hardware design and verification methodologies shows a trend towards abstraction levels higher than RTL, referred to as transaction level (TL). Transaction level models are used for early prototyping and as reference models for the verification of their RTL representation. Hence, ensuring their quality is vital for the design process. Assertion based verification (ABV) has already given a good return of investment for RTL designs. We expect the same benefit from leveraging ABV on transaction level; however mapping RTL ABV methodology directly to TL poses severe problems due to the abstraction of time and different model of computation. In this paper we present requirements for TL ABV and introduce a conceptual language for specifying TL properties. We use a simple application example for illustrating the concepts and outline a possible SystemC execution model of the conceptual language.

TLM+ modeling of embedded HW/SW systems

Virtual Prototypes (VPs) based on Transaction Level Modeling (TLM) have become a de-facto standard in todays SoC design, enabling early SW development. However, due to the growing complexity of SoC architectures full system simulations (HW+SW) become a bottleneck reducing this benefit. Hence, it is necessary to develop modeling styles which allow for further abstraction beyond the currently applied TLM methodology. This paper introduces such a modeling style, referred to as TLM+. It enables a higher modeling abstraction through merging hardware dependent driver software at the lowest level with the HW interface. Thus, sequences of HW transactions can be merged to single HW/SW transactions while preserving both the HW architecture and the low-level to high-level SW interfaces. In order to maintain the ability to validate timing-critical paths, a new resource model concept is introduced which compensates the loss of timing information, induced by merging HW transactions. Experimental results show a speed-up of up to 1000x at a timing error of approximately 10%.

Impact of Description Language, Abstraction Layer, and Value Representation on Simulation Performance

In recent years other verification features than simulation performance such as robustness and debugging gained increasing impact on simulation language and tool selection. However, fastest model execution speed is still priority number one for many design and verification engineers. This can be seen in the continuously growing interest in virtual prototypes and transaction level modeling (TLM). As part of the ongoing re-work modeling language strategies and the world wide introduction of TLM, a detailed analysis of the impact of description languages, abstraction layers and data types on simulation performance is of high importance. For the presented analysis, we considered five designs that have been modeled in VHDL, Verilog, SystemVerilog, and SystemC, using different value representations and coding styles, covering the abstraction levels from functional to behavioral to RTL. This paper presents our evaluation environment and several interesting findings of our analysis. The most important results are as follows: We found that HDL tool/language/abstraction selection of RTL models impacts on the execution speed with a factor of 4.4. We found that Verilog is on average 2times faster than VHDL for RTL models. We found that SystemC results in 10times slower RTL models than HDLs and surprisingly results in 2.6times slower TLM PV models than SystemVerilog. And we found finally that on average over all analyzed aspects SystemVerilog models are executed fastest

Specification Language for Transaction Level Assertions

Transaction level (TL) modeling is the basis of the so called electronic system level that allows development of systems on chip at a quicker pace than with classical RTL approaches. Starting from the specification phase of the product development cycle, TL modeling enables easy architecture exploration and early software co-development. In contrast to RTL, TL models (TLM) are more abstract and do not contain micro-architectural details for instance; the design focus is on high-level control and data flow. Since TLMs are essential at the decision process in early system development and as they can serve as golden reference models for later RTL regression, it is imperative to ensure that they implement the specification correctly. Assertion based verification (ABV) has given a good return of investment in RTL verification, decreasing debug time while preserving the design intent leveraging these benefits on the transaction level for the verification of TLMs requires the adaptation of current ABV approaches to the specific characteristics of these abstract models. In this paper we present an assertion specification language, based on formal definitions, that allows the specification of transaction level properties and their execution in simulation. We derive the language from known ABV languages and extend these by the required TL functionality, and explain how simulation traces of finite length can be checked against properties

Model reduction techniques for the formal verification of hardware dependent software

Contemporary researches provide many solutions for formally verifying both hardware and software systems. In this paper, we describe the formal verification of assembly programs, which are part of the HW/SW interface in hybrid systems. We have developed several methods to model assembly programs in VHDL in order to verify their functionality. Our discussion will show that, by applying different reduction methods, we managed to formally verify the correctness of iterative algorithms with execution times higher than 6000 clock cycles.

HW/SW Interface

This chapter addresses HW/SW interface implementation and modeling. As introduction, basic concepts regarding HW/SW interfaces on both HW and SW side are presented in detail. The focus is on several aspects of register and bit field read/write access, address mismatch, synchronization, and data alignment. The HW micro-architecture is outlined in block diagrams, the SW code is listed in C-code snippets. As new contributions, data flow abstraction for HW/SW models and consistently derived RTL models, TLM models, and C code by using a template approach are presented.

Requirements and Concepts for Transaction Level Assertion Refinement

Both hardware design and verification methodologies show a trend towards abstraction levels higher than RTL, referred to as transaction level (TL). Transaction level models (TLMs) are mostly used for early prototyping and as reference models for the verification of the derived RTL designs. Assertion based verification (ABV), a well known methodology for RTL models, has started to be applied on TL as well. The reuse of existing TL assertions for RTL and/or mixed level designs will especially aid in ensuring the functional equivalence of a reference TLM and the corresponding RTL design. Since the underlying synchronization paradigms of TL and RTL differ transaction events for TL, clock signals for RTL a direct reuse of these assertions is not possible. Currently there is no established methodology for refining the abstraction of assertions from TL towards RTL. In this paper we discuss the problems arising when refining TL assertions towards RTL, and derive basic requirements for a systematic refinement methodology. Building on top of an existing assertion language, we discuss some additional features for the refinement process, as well as some examples to clarify the steps involved.

Memory models for the formal verification of assembler code using bounded model checking

The formal verification of assembler code using hardware verification tools requires memory components, which e.g. hold the code itself and the processed data. Since the count of variables to be proven usually rises with both data-size and address-space, complexity boundaries of formal tools can be reached quickly. Since bounded model checking (BMC) always involves a certain time window and therefore the count of memory accesses is limited, it is possible to optimize the applied memory as far as the address-space and the size in the count of gates is concerned. In this paper we introduce various memory models, which decrease the complexity of formal proofs by applying such optimizations. We provide examples of models with limitations either of the address-space or the amount of storable data. Our analysis shows that these models remarkably enhance the performance, while verifying the instruction-set of a given processor-unit with our in-house BMC-Tool