Vu-Duc Ngo

High-rate Space-Time Block Coded Spatial Modulation

This paper presents high-rate Space-Time Block Coded SpatialModulation (STBC-SM) schemes for 4 and 6 transmit antennas. In these schemes, transmit codeword matrices are divided into two separate matrices, namely, Spatial Constellation (SC) matrix and Space-Time Block Code (STBC) matrix. The introduction of SC matrix makes it convenient in the design of STBC-SM codewords and signal detection. Simulation results are provided to demonstrate BER performance and hardware complexity in comparison with the STBC-SM in [1].

Analyzing the performance of mesh and fat-tree topologies for network on chip design

The demand of integration of many heterogeneous semiconductor intellectual property (IP) blocks has been introducing a new chip design paradigm so called on chip network. This paradigm promisingly offers a packet switched network among IPs to reduce the main problems in the very deep sub micron technologies that arise from non-scalable global wire delay, failure to achieve global synchronization, errors due to the signal integrity, non-scalable bus based functional interconnection, etc. This paper introduces interconnected or switched network topologies and also analyze their performances in terms of communication protocol related to the issues such as routing strategy, buffer size, routing algorithm , etc. The above mentioned evaluations are done by utilizing the tool that has been widely used in the research domain of computer network design, so called NS-2.

Assessing Routing Behavior on On-Chip-Network

Network-on-chip (NoC) is being proposed as a scalable and reusable communication platform for future SoC applications. An important problem in NoC design is deciding the type of routing which is one of the most crucial key factors that greatly affects the NoC architecture based systems performance. Currently, most of the proposals for routing in NoC are based upon deterministic routing mechanism because it gives better latency at low packet injection and requires less resources while guaranteeing an orderly packet arrival. However, the disadvantage of deterministic routing is that it cannot respond to dynamic network condition such as congestion. When the network becomes congested, adaptive routing provides better throughput and lower latency by allowing alternate paths. In this paper, using simulation, we evaluate the performance of adaptive routing algorithm to deterministic routing strategy respected to throughput, power consumption and latency. The simulation environment is 2D-mesh based NoC topology including different kinds of mapping video object plane decoder (VOPD) application onto this architecture. The experiment results prove the adaptive routing performance under network congestion occurrence

Multiplane Virtual Channel Router for Network-on-Chip Design

Network-on-chip is alternative paradigm to improve communication bandwidth compared to bus-based communication, and its performance largely depends on architecture of router. In this paper, multiplane virtual-channel router which has multiple crossbar switches and modified switch allocator is proposed to enhance the latency and throughput performance. Theoretically, we show this multiplane router has much better latency performance compare to single plane router. Also, we carry out the RTL simulation in order to show that the multiplane router with small number of virtual-channels offering smaller hardware complexity than single plane router with large number of virtual-channels.

On chip network: topology design and evaluation using NS2

The demand of integration of many heterogeneous semiconductor intellectual property (IP) blocks has been introducing a new chip design paradigm so called on chip network. This paradigm promisingly offers a packet switched network among IPs to reduce the main problems in the ultra deep submicron technologies that arise from nonscalable global wire delay, failure to archive global synchronization, errors due to signal integrity, nonscalable bus based functional interconnection, etc. In this paper, we introduce interconnected or switched network topologies and also analyze their performances in terms of communication protocol related to the issues such as routing strategy, buffer size, routing algorithm. The above mentioned evaluations are done by utilizing the tool that has been widely used in the research domain of computer network design, so called NS2

Realization of video object plane decoder on on-chip network architecture

System-on-chip (SoC) designs provide integrated solutions to challenging design problems in the telecommunications, multimedia, and so on. Present and future SoC are designed using pre-existing components which we call cores. Communication between the cores will become a major bottleneck for system performance as standard hardwired bus-based communication architectures will be inefficient in terms of throughput, latency and power consumption. To solve this problem, a packet switched platform that considers the delay and reliability issues of wires so called Network-on-Chip (NoC) has been proposed. In this paper, we present interconnected network topologies and analyze their performances with a particular application under bandwidth constrains. Then we compare the performances among different ways of mapping the cores onto a Mesh NoC architecture. The comparison between Mesh and Fat-Tree topology is also presented. These evaluations are done by utilizing NS-2, a tool that has been widely used in the computer network design.

The optimum network on chip architectures for video object plane decoder design

On Chip Network (OCN) has been proposed as a new methodology for addressing the design challenges of future massly integrated system in nanoscale. In this paper, three differently heterogenous Tree-based network topologies are proposed as the OCN architectures for Video Object Plane Decoder (VOPD). The topologies are designed in order to maximize the system throughput. This paper also evaluates the proposed topologies by comparing them to other conventional topologies such as 2-D Mesh and Fat-Tree with respects to throughput, power consumption and size. We use the power modelling tool, known as Orion model to calculate the static powers, areas, and dynamic energies of three topologies. The experiment results show that our Tree-based topologies offer similar throughputs as Fat-Tree does and much higher throughputs compared to 2-D Mesh while use less chip areas and power consumptions.

Performance and complexity analysis of credit-based end-to-end flow control in network-on-chip

Network-on-Chip is an alternative paradigm to improve communication bandwidth compared to bus-based communication, and its performance degrades if there is no effective flow control method., Heterogeneous networks with very slow processing elements (PEs) especially need a flow control mechanism at the transport layer to prevent too much packet injection. In this paper, a credit-based end-to-end flow control (CB-EEFC) is implemented to control the network latency at high traffic loads. Simulation in mesh networks shows improved performance in latency and 0.5% up to 3% saturated throughput decrease with the CB-EEFC method. RTL gate level simulation shows that a network interface using CB-EEFC brings about a 31.4% increase in complexity compared to a network interface without CB-EEFC.

Realizing Network on Chip Design of H.264 Decoder Based on Throughput Aware Mapping

A new chip design era in the coming nano-scale, so called network on chip (NoC), has been introduced based on the demand of the intensive use and seamless integration of many heterogeneous semiconductor intellectual property (IP) blocks in the form of embedded and distributed processors, memories, DSPs, and interfaces. The NoC design, with its own characteristics, very strictly requires the satisfaction of several physical constraints such as the network latency, the used area as well as the power consumption of design. In this paper, we introduce the queuing theory based and power model based of the router in order to analyzes the throughput, size and energy consumption of heterogeneous network on chip architectures. This article also presents the method to automatically map IPs onto the given architectures to obtain the maximum throughput while keep the minimum energy consumption. Some realizations of H.264 decoder on regular NoC architectures such as 2D mesh and fat-tree are simulated. The results show that the network throughput is maximized with the optimized mapping scheme. The energy dissipation consequently calculated and shown that it is very much saved compared to that of random mapping.

A novel Spatially-Modulated Orthogonal Space-Time Block Code for 4 transmit antennas

This paper presents a novel Spatially Modulated Orthogonal Space-Time Block Coding (SM-OSTBC) scheme for 4 transmit antennas based on the concept of Spatial Constellation (SC) first proposed in [1]. In the scheme, transmit SM-OSTBC codewords are generated simply by multiplying SC codewords with OSTBC codewords. An optimization technique for the SM-OSTBC scheme to achieve a transmit diversity order of 3 is discussed. In addition, a simple maximum-likelihood (ML) decoder is derived. BER performance of the proposed scheme is evaluated via computer simulation and theoretical upper bound. It is shown that the proposed scheme outperforms various existing MIMO transmission counterparts in a number of application scenarios.