Walter Aloisi

Efficiency model of boost dc-dc PWM converters

A thorough efficiency analysis of a boost PWM converter taking into account the conduction losses, the diode power loss, the switching losses, the gate-drive loss and the capacitive switching loss, for both continuous conduction mode and discontinuous conduction mode is presented. The analysis is extended in the synchronous rectification case where a self driven transistor instead of the diode rectifier is adopted. The expressions of the converter efficiency can be used to predict the circuit behaviour for both a constant input and constant output voltage operation. The model has been validated using SPECTRE simulator and a 0.35 µm CMOS process, and error always lower than 2% were found. Copyright

Gated-Clock Design of Linear-Feedback Shift Registers

In this paper, we will present a method to reduce the power consumption of the popular linear feedback shift register. The proposed scheme is based on the gated clock design approach and it can offer a significant power reduction, depending on technological characteristics of the employed gates. Moreover, the analytical condition that must be satisfied to achieve a power reduction of the gated-clock circuit has been found. Theoretical analysis was validated through many transistor-level SPECTRE simulations in CADENCE environment by using the 0.35- mum digital standard cells technology supplied by AMS. Simulation results have shown a power reduction of about 10% with a mean error of about 3% with respect to theoretical derivations.

Design and comparison of very low-voltage CMOS output stages

This paper analyzes and compares CMOS output stages for very low-voltage operational amplifiers. The analysis was carried out by taking into account output stage performance parameters which also affect the characteristics of the overall amplifier. In particular, three quality factors were defined to afford the designer a better understanding of the relationships between current dissipation, area consumption, bandwidth, and linearity. Exploiting these new parameters, four output stages were analyzed in detail and compared. Finally, comparison results were validated by simulations.

Exploiting the high-frequency performance of low-voltage low-power SC filters

This paper investigates the design of low-voltage low-power switched-capacitor (SC) filters for high-frequency applications by using the clock-booster approach. In particular, our proposed SC filter architecture uses single-ended double-sampling integrator cells based on low-voltage operational transconductance amplifiers which take advantage of dynamic biasing and the clock-booster technique to drive the switch transistors. To validate its high-frequency capability, two low-pass elliptic SC filters respectively with a corner frequency of 6 and 8-MHz, were designed in a 0.35-/spl mu/m CMOS process. Both are suitable for telecom applications and can operate with a power supply as low as 1.5 V, while dissipating 11 mW. Measurements showed that for an output amplitude of 1 V/sub pp/, their total harmonic distortions were maintained well below -40 dB in their bandwidths. Comparisons with other SC filter implementations in the literature, which highlight the quality of our implementation are also provided.

Analysis and optimization of gain-boosted telescopic amplifiers

A thorough analysis of the behavior of a simple gain-boosted telescopic amplifier in terms of both the frequency and time domain is performed. The well-known slow-settling component is analyzed and a constraint for eliminating its effect is also given. Moreover, a procedure for designing the amplifier, based on the comparison of its time response to the time response of a two-pole system is reported, too.

Miller Compensation: Optimization with Current Buffer/Amplifier

A novel design-oriented approach for Miller compensation exploiting current buffer/amplifiers is described. The analysis enables a simple design procedure to be outlined, which is in turn applied to a two-stage CMOS OTA driving a large capacitive load. Assuming a 100-pF load, three example compensation networks were designed using alternatively a compensation capacitor as low as 1.3 pF, 0.6 pF and 250 fF. Simulations in very good agreement with theoretical results are also given.

Low-voltage linear voltage regulator suitable for memories

In this communication a low-voltage linear voltage regulator in CMOS technology is presented. It is based on a two class-AB gain stage and, hence, does not suffer from internal slew-rate limitation when very large load capacitances are used. The linear regulator suitable for memory application was designed in a 0.35 /spl mu/m standard CMOS technology. The regulator can work with a no-regulated input voltage in the range from 1.3 V to 3 V providing a regulated voltage of 1 V with a load capacitance of 2.2 nF.

Design of low-voltage low-power SC filters for high-frequency applications

In this communication an approach for designing low-voltage and low-power SC filters for high-frequency applications is presented. It is based on the use of single-ended double-sampling integrator cells based on low-voltage operational transconductance amplifiers which take advantage of a dynamic biasing and a clock booster. Following the proposed approach, a 6-MHz low-pass elliptic SC filter was designed in a 0.35-/spl mu/m CMOS process. The filter exhibits a 1.5-dB in-band ripple and a stopband attenuation of -35 dB while powered with 1.5-V power supply. The die size is 0.29 mm/sup 2/ while dissipating only 11 mW.

Analysis, modelling and optimization of a gain boosted telescopic amplifier

In this paper, a thorough analysis of a gain-boosted telescopic amplifier (GBTA) is presented and a systematic design procedure for optimizing its time response will be given. Specifically, the GBTA closed-loop time response will be analysed in detail and the constraints eliminating the well-known ‘slow settling component’ found. Subsequently, an optimization strategy based on the comparison between the GBTA time response and the time response of a pure two-pole amplifier (referred to as the target system) will be described. This strategy allows the designer to develop a GBTA starting from the target system specifications in a simple and systematic way. The proposed procedure has been validated by means of simulations and excellent agreement found between the simulated and the expected results. Copyright

Analysis and optimization of a low-voltage class-AB output stage

In this communication an approach for analyzing and designing low-power CMOS output stages is proposed. The optimization is carried out by taking into account output stage performance parameters which also affect main characteristics of the overall amplifier. To this aim, three quality factors are defined to afford the designer a better understanding of the relationships between current dissipation, area consumption, bandwidth and linearity.