Yujin Seo

Alleviation of fermi-level pinning effect at metal/germanium interface by the insertion of graphene layers

In this paper, we report the alleviation of the Fermi-level pinning on metal/n-germanium (Ge) contact by the insertion of multiple layers of single-layer graphene (SLG) at the metal/n-Ge interface. A decrease in the Schottky barrier height with an increase in the number of inserted SLG layers was observed, which supports the contention that Fermi-level pinning at metal/n-Ge contact originates from the metal-induced gap states at the metal/n-Ge interface. The modulation of Schottky barrier height by varying the number of inserted SLG layers (m) can bring about the use of Ge as the next-generation complementary metal-oxide-semiconductor material. Furthermore, the inserted SLG layers can be used as the tunnel barrier for spin injection into Ge substrate for spin-based transistors.

Effective Schottky Barrier Height Lowering of Metal/n-Ge with a TiO2/GeO2 Interlayer Stack

A perfect ohmic contact formation technique for low-resistance source/drain (S/D) contact of germanium (Ge) n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) is developed. A metal-interlayer-semiconductor (M-I-S) structure with an ultrathin TiO2/GeO2 interlayer stack is introduced into the contact scheme to alleviate Fermi-level pinning (FLP), and reduce the electron Schottky barrier height (SBH). The TiO2 interlayer can alleviate FLP by preventing formation of metal-induced gap states (MIGS) with its very low tunneling resistance and series resistance and can provide very small electron energy barrier at the metal/TiO2 interface. The GeO2 layer can induce further alleviation of FLP by reducing interface state density (Dit) on Ge which is one of main causes of FLP. Moreover, the proposed TiO2/GeO2 stack can minimize interface dipole formation which induces the SBH increase. The M-I-S structure incorporating the TiO2/GeO2 interlayer stack achieves a perfect ohmic characteristic, which has proved unattainable with a single interlayer. FLP can be perfectly alleviated, and the SBH of the metal/n-Ge can be tremendously reduced. The proposed structure (Ti/TiO2/GeO2/n-Ge) exhibits 0.193 eV of effective electron SBH which achieves 0.36 eV of SBH reduction from that of the Ti/n-Ge structure. The proposed M-I-S structure can be suggested as a promising S/D contact technique for nanoscale Ge n-channel transistors to overcome the large electron SBH problem caused by severe FLP.

Effect of Hydrogen Annealing on Contact Resistance Reduction of Metal–Interlayer–n-Germanium Source/Drain Structure

The effect of post-deposition H2 annealing (PDHA) on the reduction of a contact resistance by the metal-interlayer-semiconductor (M-I-S) source/drain (S/D) structure of the germanium (Ge) n-channel field-effect transistor (FET) is demonstrated in this letter. The M-I-S structure reduces the contact resistance of the metal/n-type Ge (n-Ge) contact by alleviating the Fermi-level pinning (FLP). In addition, the PDHA induces interlayer doping and interface controlling effects that result in a reduction of the tunneling resistance and the series resistance regarding the interlayer and an alleviation of the FLP, respectively. A specific contact resistivity (pc) of 3.4×10-4Ω·cm2 was achieved on a moderately doped n-Ge substrate (1×1017 cm-3), whereby 5900× reduction was exhibited from the Ti/n-Ge structure, and a 10× reduction was achieved from the Ti/Ar plasma-treated TiO2-x/n-Ge structure. The PDHA technique is, therefore, presented as a promising S/D contact technique for the development of the Ge n-channel FET, as it can further lower the contact resistance of the M-I-S structure.

The Mechanism of Schottky Barrier Modulation of Tantalum Nitride/Ge Contacts

In this letter, we discuss the mechanism of Schottky barrier height (SBH) modulation of the TaN/Ge contact by varying the nitrogen concentration in the TaN. The Fermi level, which is strongly pinned near the valence band edge of Ge, moves to the conduction band edge of Ge with higher nitrogen concentration in the reactive sputtered TaN. This SBH modulation is attributed to the presence of an electric dipole induced by Ge-N bonds at the interface of the TaN/Ge contact. This SBH modulation due to the semiconductor-nitrogen bonds at the interface is not specific to TaN/Ge, but rather is a general feature in various transition-metal nitride systems on various semiconductors.

Demonstration of Ge pMOSFETs with 6 Å EOT using TaN/ZrO 2 /Zr-cap/n-Ge(100) gate stack fabricated by novel vacuum annealing and in-situ metal capping method

The superior gate stack was fabricated by employing novel high vacuum annealing followed by in-situ metal capping method to suppress GeO_x regrowth. Less GeO volatilization induces less Ta diffusion into gate oxide which reduces leakage current and enables further scaling. With ZrO₂/Zr-cap stack, highly scaled Ge (100) pMOSFETs have been demonstrated which shows extremely low EOT (6.06 Å), low gate leakage current of 250 nA/cm²@|V_g-V_FB|=1V, superior SS of 70 mV/dec, and 110 cm²/Vs of peak hole mobility.

The Work Function Behavior of Aluminum-Doped Titanium Carbide Grown by Atomic Layer Deposition

The effective work function (eWF) of Al-doped titanium carbide (TiAlC) metal electrodes prepared by atomic layer deposition shows a strong dependence on the underlying gate dielectrics. The eWF of TiAlC on HfO2 shows a low value of 4.2 eV independent of the deposition temperature and process conditions, whereas that on SiO2 shifted to a midgap value of 4.7 eV, and it was sensitive to the process conditions. The mechanism underlying this TiAlC work function dependence on different gate dielectrics is investigated in detail.

The Impact of an Ultrathin Y 2 O 3 Layer on GeO 2 Passivation in Ge MOS Gate Stacks

This paper investigates the impact of an atomic layer-deposited Y₂O₃ dielectric on the passivation of a GeO₂ layer in GeO₂-based Ge gate stacks. The equivalent oxide thickness scalability and thermal stability of the ultrathin Y₂O₃ layer are evaluated at different Y₂O₃ thicknesses and annealing conditions in detail. Experimental results show that a Y₂O₃ layer thickness of 1.0 nm is required to serve as a GeO₂ passivation layer while retaining gate-stack performance at 400 °C postdeposition annealing. However, at a higher annealing temperature of 500 °C, the barrier property deteriorates and allows GeO desorption. The proposed gate-stack implies the applicability of a Y₂O₃ passivation method for further scaled GeO₂-based Ge gate stacks.

Very Low-Work-Function ALD-Erbium Carbide (ErC 2 ) Metal Electrode on High-

Erbium carbide (ErC2) prepared by atomic layer deposition (ALD) is successfully demonstrated for the first time as a novel work function (WF) metal for nMOSFET applications. The prepared ErC2 shows a very low effective WF (eWF), as low as 3.9 eV on HfO2, yet with excellent thermal stability. In addition, it did not show significant Fermi-level pinning on high-k dielectrics even after high-temperature annealing. The low eWF property of ErC2 originates from the properties of the lanthanide family, while its good thermal stability is attributed to the properties of metal carbides. ALD-ErC2 has superior conformality over other deposition methods, and thus is a strong candidate for 3-D structure devices.

K

Aluminum oxynitride (AlON) is investigated as a germanium oxide (GeO) desorption barrier layer for Ge MOSFETs. Interface and border traps in the AlON/GeO₂/Ge gate-stack are discussed in detail and compared with those in the Al₂O₃/GeO₂/Ge gate-stack via MOS and MOSFET structures. Although the interface traps remain the same for AlON and Al₂O₃ in the gate stacks, the AlON gate-stack exhibits a reduced border trap, which results in improved reliability over the Al₂O₃ gate-stack. This is supported by both the charge-trapping and low-frequency noise analyses.

Dielectrics

A new method of forming an ohmic contact without an increase in parasitic resistance is proposed in the Ti/GeO2/Ge substrate. Fermi-level depinning in Ti/GeO2/n–Ge contacts is possible with the formation of an interfacial TiOx layer in the contacts via an interfacial reaction. Unlike the intentional deposition of a metal oxide on a Ge substrate, this method provides easy process integration to lessen Fermi-level pinning in n-type Ge substrates.