Wanghua Wu

A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS

A mm-wave digital transmitter based on a 60 GHz all-digital phase-locked loop (ADPLL) with wideband frequency modulation (FM) for FMCW radar applications is proposed. The fractional-N ADPLL employs a high-resolution 60 GHz digitally-controlled oscillator (DCO) and is capable of multi-rate two-point FM. It achieves a measured rms jitter of 590.2 fs, while the loop settles within 3 μs. The measured reference spur is only -74 dBc, the fractional spurs are below -62 dBc, with no other significant spurs. A closed-loop DCO gain linearization scheme realizes a GHz-level triangular chirp across multiple DCO tuning banks with a measured frequency error (i.e., nonlinearity) in the FMCW ramp of only 117 kHz rms for a 62 GHz carrier with 1.22 GHz bandwidth. The synthesizer is transformer-coupled to a 3-stage neutralized power amplifier (PA) that delivers +5 dBm to a 50 Ω load. Implemented in 65 nm CMOS, the transmitter prototype (including PA) consumes 89 mW from a 1.2 V supply.

High-Resolution Millimeter-Wave Digitally Controlled Oscillators With Reconfigurable Passive Resonators

Two new millimeter-wave digitally controlled oscillators (DCOs) that achieve a tuning range >10% and fine frequency resolution 1 MHz simultaneously are described. Switched metal capacitors distributed across a passive resonator tune the oscillation frequency. To obtain sub-MHz frequency resolution, tuning step attenuation techniques exploiting an inductor and a transformer are proposed. Two 60-GHz implementations, a fine-resolution inductor-based DCO (L-DCO) and a transformer-coupled DCO (T-DCO), are demonstrated in 90-nm CMOS. The phase noise of both DCOs is lower than -90.5 dBc/Hz at 1-MHz offset across 56-62 GHz. The T-DCO achieves a fine frequency tuning step of 2.5 MHz, whereas the L-DCO tuning step is over one order of magnitude finer at 160 kHz. The L-DCO and T-DCO consume 10 and 12 mA, respectively, from a 1.2-V supply. The size of each DCO core is 0.4 ×0.4 mm2.

Passive Circuit Technologies for mm-Wave Wireless Systems on Silicon

The performance characteristics of transmission lines, silicon integrated waveguides, tunable LC resonators and passive combiners/splitters and baluns are described in this paper. It is shown that Q-factor for an on-chip LC tank peaks between 20 and 40 GHz in a 65 nm RF-CMOS technology; well below the bands proposed for many mm-wave applications. Simulations also predict that the Q-factor of differential CPW transmission lines on-chip can exceed 20 at 60 GHz in RF-CMOS when a floating shield is applied, outperforming unshielded variants employing more advanced metal stacks. A PA circuit demonstrator for advanced on-chip passive power combiners, splitters and baluns realizes peak-PAE of 18% and Psat better than 20 dBm into a 50 Ω load at 62 GHz. An outlook to the enablement of digitally intensive mm-wave ICs and low-loss passive interconnections (0.15 dB/mm measured loss at 100 GHz) concludes the paper.

A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS

Frequency synthesis at mm-Waves is still dominated by analog PLLs, although all-digital PLLs (ADPLLs) [1] have been widely explored below 10GHz. The major obstacle has been the poor quality of digitally controlled oscillators (DCO) as MOS varactor Q-factor drops to <;10 at 60GHz. A mm-Wave digital transmitter (TX) based on a 60GHz fractional-N ADPLL with two-point FM is proposed here. The TX features extensive reconfigurability and permits the highest degree of integration of RF and baseband circuitry for low-cost, high-volume applications. To simplify the TX architecture, the synthesizer is capable of FM, hence a time-to-digital converter (TDC) is preferred over bang-bang phase detection. With the aid of autonomous calibrations of DCO and TDC gain, wideband two-point FM is achieved.

A mm-Wave FMCW radar transmitter based on a multirate ADPLL

We present a 60-GHz FMCW radar transmitter based on an all-digital phase-locked loop (ADPLL) with ultra-wide linear frequency modulation. Multirate, two-point modulation generates an ultra-linear programmable frequency ramp. A novel, closed-loop DCO gain linearization method employing 24kb of SRAM realizes a GHz-level triangular chirp with high sweep linearity, and enables hitless modulation through multiple DCO tuning banks. Measured frequency error (i.e., nonlinearity) in the FMCW ramp is only 117-kHzrms for a 62-GHz carrier with 1.22-GHz bandwidth. The synthesizer is transformercoupled to a 3-stage neutralized power amplifier that delivers +5 dBm to a 50-Ω load. Implemented in 65-nm CMOS, the transmitter prototype consumes 89 mW from a 1.2-V supply.

Energy-efficient wireless front-end concepts for ultra lower power radio

Two ultra low power wireless concepts are described in this paper. A high data rate receiver demonstrator consisting of LNA, sub-harmonic I/Q mixer and transimpedance IF amplifiers realizes an energy consumption of 1.75 nJ/bit at 10 Mbit/s in the 17 GHz band. A high-band FM-UWB receiver demonstrator, which achieves a measured sensitivity of -84.3 dBm at 100 kbit/s while consuming just 6 mW is also described.

A digital ultra-fast acquisition linear frequency modulated PLL for mm-wave FMCW radars

We propose a new digitally-intensive frequency synthesizer for a 60 GHz wireless sensing FMCW radar system and verify it though detailed circuit-level and system-level simulations. It consists of a 20 GHz digital PLL and a frequency tripler. The 20 GHz digital PLL features ultra-fast acquisition (less than 5 μs) and low phase noise (-80 dBc/Hz at 100 kHz offset) by adopting dynamic and hitless loop bandwidth control. Linear frequency modulation (LFM) produces a triangle-shaped chirp signal with 3.2 GHz bandwidth in a 2 ms sweep. The maximum frequency deviation is only 0.014% of the chirp bandwidth. A multiplier following the 20 GHz PLL extends the LFM bandwidth to 9.6 GHz centered at 60 GHz, resulting in a range resolution better than 5 cm.

High-resolution 60-GHz DCOs with reconfigurable distributed metal capacitors in passive resonators

Mm-wave digitally-controlled oscillators (DCOs) with reconfigurable passive resonators are proposed, which achieve wide tuning range (>;10%) and fine frequency resolution (<;1 MHz) simultaneously. Two 60-GHz implementations: a fine-resolution inductor-based DCO (L-DCO) and a transformer-based DCO (T-DCO) are demonstrated in 90-nm CMOS, exploiting metal capacitors only for frequency tuning. Both DCOs obtain >;9.7% linear tuning range and phase noise lower than -90.5 dBc/Hz at 1-MHz offset across the 56-62 GHz range. The T-DCO achieves fine frequency tuning step of 2.5 MHz, whereas that of the L-DCO is better than 160 kHz. The L-DCO and T-DCO consume 10 mA and 12 mA, respectively, from a 1.2-V supply. The core size of each DCO is 0.4×0.4 mm2.

17 GHz RF Front-Ends for Low-Power Wireless Sensor Networks

A 17 GHz low-power radio transceiver front-end implemented in a 0.25 mum SiGe:C BiCMOS technology is described. Operating at data rates up to 10 Mbit/s with a reduced transceiver turn-on time of 2 mus, gives an overall energy consumption of 1.75 nJ/bit for the receiver and 1.6 nJ/bit for the transmitter. The measured conversion gain of the receiver chain is 25-30 dB into a 50 Omega load at 10 MHz IF, and noise figure is 12 plusmn0.5 dB across the band from 10 to 200 MHz. The 1-dB compression point at the receiver input is -37 dBm and IIP3 is -25 dBm. The maximum saturated output power from the on-chip transmit amplifier is -1.4 dBm. Power consumption is 17.5 mW in receiver mode, and 16 mW in transmit mode, both operating from a 2.5 V supply. In standby, the transceiver supply current is less than 1 muA.

17GHz RF Front-Ends for Low-Power Wireless Sensor Networks

A 17 GHz low power radio front-end is presented. Low-power operation is based on minimization of energy/bit, the design metric for low-power radios. Increasing the data rate while reducing the receiver turn-on time is proposed as a method of improving energy efficiency. Circuit design of prototype receiver and transmitter front ends for a 17 GHz ultra low-power radio are presented and discussed. The power gain of the LNA is 12 dB with a minimum noise figure of 3.25 dB. Conversion gain of the RF chain is 30 dB at DC, the measured IIP3 of the Rx chain is -26.3 dBm whereas the maximum saturated output power of the PA is about 5 dBm. The total, measured power consumption is 17.5 mW (@2.5 supply) in the received