John R. Long

Monolithic transformers for silicon RF IC design

A comprehensive review of the electrical performance of passive transformers fabricated in silicon IC technology is presented. Two types of transformer construction are considered in detail, and the characteristics of two-port (1:1 and 1:n turns ratio) and multiport transformers (i.e., baluns) are presented from both computer simulation and experimental measurements. The effects of parasitics and imperfect coupling between transformer windings are outlined from the circuit point of view. Resonant tuning is shown to reduce the losses between input and output at the expense of operating bandwidth. A procedure for estimating the size of a monolithic transformer to meet a given specification is outlined, and circuit examples are used to illustrate the applications of the monolithic transformer in RF ICs.

The modeling, characterization, and design of monolithic inductors for silicon RF IC's

The results of a comprehensive investigation into the characteristics and optimization of inductors fabricated with the top-level metal of a submicron silicon VLSI process are presented. A computer program which extracts a physics-based model of microstrip components that is suitable for circuit (SPICE) simulation has been used to evaluate the effect of variations in metallization, layout geometry, and substrate parameters upon monolithic inductor performance. Three-dimensional (3-D) numerical simulations and experimental measurements of inductors were also used to benchmark the model accuracy. It is shown in this work that low inductor Q is primarily due to the restrictions imposed by the thin interconnect metallization available in most very large scale integration (VLSI) technologies, and that computer optimization of the inductor layout can be used to achieve a 50% improvement in component Q-factor over unoptimized designs.

A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-/spl mu/m CMOS

A low-noise amplifier (LNA) uses low-loss monolithic transformer feedback to neutralize the gate-drain overlap capacitance of a field-effect transistor (FET). A differential implementation in 0.18-/spl mu/m CMOS technology, designed for 5-GHz wireless local-area networks (LANs), achieves a measured power gain of 14.2 dB, noise figure (NF, 50 /spl Omega/) of 0.9 dB, and third-order input intercept point (IIP3) of +0.9 dBm at 5.75 GHz, while consuming 16 mW from a 1-V supply. The feedback design is benchmarked to a 5.75-GHz cascode LNA fabricated in the same technology that realizes 14.1-dB gain, 1.8-dB NF, and IIP3 of +4.2 dBm, while dissipating 21.6 mW at 1.8 V.

A low-voltage 5.1-5.8-GHz image-reject downconverter RF IC

This paper describes a single-chip implementation of a low-voltage image-reject downconverter for a 5.1-5.8-GHz radio receiver. It consists of a low-noise preamplifier (LNA) that is simultaneously noise and power matched to the RF source, and dual doubly balanced mixers coupled to the LNA by a monolithic trifilar transformer. The image-reject architecture eliminates an RF filter, thereby simplifying packaging requirements. The downconverter realizes over 36 dB of image rejection while dissipating 24 mW from a 0.9 V supply, or 18.5 mW at 1.8 V. Conversion gain is 14 dB, IIP3=-5.5 dBm, and noise figure is 6.8 dB (single sideband 50 /spl Omega/) when operating from a 0.9 V supply.

A Q-factor enhancement technique for MMIC inductors

An increase of 50% in the peak Q-factor and a wider operating bandwidth for monolithic inductors is achieved by exciting a microstrip structure differentially. Conventional excitation of a 8 nH spiral inductor fabricated in a production silicon IC technology resulted in a peak (measured) Q-factor of 6.6 at 1.6 GHz, while the differential connection showed a maximum Q-factor of 9.7 at 2.5 GHz. These experimental results compared favorably with the behaviour predicted from simulation.

A 10-Gb/s CDR/DEMUX with LC delay line VCO in 0.18-/spl mu/m CMOS

A monolithic 10 Gb/s clock/data recovery and 1:2 demultiplexer is implemented in 0.18 /spl mu/m CMOS. The quadrature LC delay line oscillator has 110 MHz tuning range and 60 MHz/V sensitivity to power-supply pulling. The circuit meets SONET OC-192 requirements with 1 ps rms measured jitter. The 1.9/spl times/1.5 mm/sup 2/ IC consumes 285 mW from a 1.8 V supply.

Modeling, characterization and design of monolithic inductors for silicon RFICs

The results of a comprehensive investigation into the characteristics and optimization of inductors fabricated in the top-level metal of a sub-micron silicon VLSI process are presented. A computer program which extracts a physically-based model of microstrip components which is suitable for circuit (SPICE) simulation has been used to evaluate variations in metallization, layout geometry and substrate parameters upon inductor performance. 3-D numerical simulations and experimental measurements of inductors were also used to benchmark the model accuracy. It is shown in this work that low inductor Q is primarily due to the restrictions imposed by the thin interconnect metallization available in most VLSI technologies, and that computer optimization of the inductor layout can be used to achieve a 50% improvement in component Q-factor over unoptimized designs.

RF analog and digital circuits in SiGe technology

The performance of a commercially viable SiGe-HBT technology is demonstrated in analog and digital communications applications. The measurements show that circuits fabricated in this technology are capable of fulfilling application requirements for RF analog in the 1-5 GHz range and for high-speed digital circuits at or above the 10 Gb/s range, with potentially lower power, lower cost and higher reliability compared to other high-speed/RF technology options.

A 2 V 5.1-5.8 GHz image-reject receiver with wide dynamic range

A 5-6 GHz image-reject receiver IC implemented in 0.5 /spl mu/m 25 GHz silicon bipolar technology draws 20 mA from a 2 V supply. The image rejection obtainable with this IC is sufficient to eliminate the off-chip interstage RF filter in a heterodyne receiver, thereby simplifying packaging requirements and decreasing costs. The methods used here that make this design possible are: regenerative frequency doubling, I-Q phase error compensation and RF interstage coupling. Low-voltage circuit topologies are used throughout to minimize power consumption and ensure compatibility with deep sub-micron CMOS (baseband) ASICs operating from low-voltage supplies.

A 5.1-5.8 GHz low-power image-reject downconverter in SiGe technology

A 5.1-5.8 GHz downconverter realizes over 36 dB of image rejection while dissipating 24 mW from a 0.9 V supply, or 18.5 mW at 1.8 V. Conversion gain is 14 dB, IIP3=-5.5 dBm and SSB noise figure (50/spl Omega/) is 6.8 dB at 0.9 V. The circuit is realized in a 0.5 /spl mu/m SiGe bipolar technology.