Warren Jackson

A polymer/semiconductor write-once read-many-times memory

Organic devices promise to revolutionize the extent of, and access to, electronics by providing extremely inexpensive, lightweight and capable ubiquitous components that are printed onto plastic, glass or metal foils. One key component of an electronic circuit that has thus far received surprisingly little attention is an organic electronic memory. Here we report an architecture for a write-once read-many-times (WORM) memory, based on the hybrid integration of an electrochromic polymer with a thin-film silicon diode deposited onto a flexible metal foil substrate. WORM memories are desirable for ultralow-cost permanent storage of digital images, eliminating the need for slow, bulky and expensive mechanical drives used in conventional magnetic and optical memories. Our results indicate that the hybrid organic/inorganic memory device is a reliable means for achieving rapid, large-scale archival data storage. The WORM memory pixel exploits a mechanism of current-controlled, thermally activated un-doping of a two-component electrochromic conducting polymer.

High-performance flexible zinc tin oxide field-effect transistors

Flexible transistors were fabricated by sputter deposition of zinc tin oxide (ZTO) onto plasma-enhanced chemical vapor deposition gate dielectrics formed on flexible polyimide substrates with a blanket aluminum gate electrode. The flexible transistors exhibited high on-currents of 1mA, on/off ratios of 106, subthreshold voltage slopes of 1.6V/decade, turn-on voltages of −17V, and mobilities of 14cm2V−1s−1. Capacitance measurements indicate that the threshold voltage and subthreshold slope are primarily influenced by residual doping in the ZTO rather than by defects at the semiconductor/dielectric interface, and are useful for assessing contact resistance.

Electrochromic conductive polymer fuses for hybrid organic/inorganic semiconductor memories

We demonstrate a nonvolatile, write-once-read-many-times (WORM) memory device employing a hybrid organic/inorganic semiconductor architecture consisting of thin film p-i-n silicon diode on a stainless steel substrate integrated in series with a conductive polymer fuse. The nonlinearity of the silicon diodes enables a passive matrix memory architecture, while the conductive polyethylenedioxythiophene:polystyrene sulfonic acid polymer serves as a reliable switch with fuse-like behavior for data storage. The polymer can be switched at ∼2 μs, resulting in a permanent decrease of conductivity of the memory pixel by up to a factor of 103. The switching mechanism is primarily due to a current and thermally dependent redox reaction in the polymer, limited by the double injection of both holes and electrons. The switched device performance does not degrade after many thousand read cycles in ambient at room temperature. Our results suggest that low cost, organic/inorganic WORM memories are feasible for light weight...

Area-Dependent Switching in Thin Film-Silicon Devices

We report on the area dependence of switching in both Cr/ p + a-Si:H/Ag(Al) and Cr/ p + μc-Si/Ag(Al) filament switches. The doped amorphous (a-Si:H) or microcrystalline (μc-Si) thin Si layers are made by hot-wire chemical vapor deposition. The device active region area (A) is varied over 5 orders of magnitude, from 10 -7 to 10 -2 cm 2 , using photolithographically defined Ag and Al top contacts. Before switching, the resistance of 100-μm 2 devices is normally about 100 kΩ for μc-Si and 10 GΩ for a-Si:H. After switching with applied current ramps, the resistance decreases to a few hundred ohms in all a-Si devices and to a few thousands ohms in μc-Si devices. In both μc-Si and a-Si:H devices, the switching voltage (V sw ) decreases with increasing device area according to V sw ~ V 0 -αln(A/A 0 ) with α=0.3V for a-Si:H and α=0.04V for μc-Si. For both materials, the switching current roughly obeys the power law I sw ∞ A β with β~1. A statistical model is proposed to explain the area scaling of the switching voltage and relate the parameters to the material properties.

Roll-to-roll manufacturing of electronics on flexible substrates using self-aligned imprint lithography (SAIL)

Abstract— The manufacture of large-area arrays of thin-film transistors on polymer substrates using roll-to-roll (R2R) processes exclusively is being developed. Self-aligned imprint lithography (SAIL) enables the patterning and alignment of submicron-sized features on meter-scaled flexible substrates in the R2R environment. SAIL solves the problem of precision interlayer registry on a moving web by encoding all the geometry information required for the entire patterning steps into a monolithic three-dimensional imprint with discrete thickness modulation. The pre-aligned multiple-step mask structure maintains its alignment regardless of subsequent substrate distortion. Challenges are encountered in relation to the novel nature of using flexible substrates and building toolsets for the R2R processing. In this paper, methods of the SAIL process, the resulting active-matrix backplanes, the trajectory of SAIL process development, and the remaining issues for production are presented.

Trilayer Tunnel Selectors for Memristor Memory Cells

An integrated memory cell with a memristor and a trilayer crested barrier selector, showing repeatable nonlinear current–voltage switching loops is presented. The fully atomic‐layer‐deposited TaN1+x/Ta2O5/TaN1+x crested barrier selector yields a large nonlinearity (>104), high endurance (>108), low variability, and low temperature dependence.

Advances in roll-to-roll imprint lithography for display applications

A solution to the problems of roll-to-roll lithography on flexible substrates is presented. We have developed a roll-toroll imprint lithography technique to fabricate active matrix transistor backplanes on flexible webs of polyimide that have a blanket material stack of metals, dielectrics, and semiconductors. Imprint lithography produces a multi-level 3- dimensional mask that is then successively etched to pattern the underlying layers into the desired structures. This process, Self-Aligned Imprint Lithography (SAIL), solves the layer-to-layer alignment problem because all masking levels are created with one imprint step. The processes and equipment required for complete roll-to-roll SAIL fabrication will be described. Emphasis will be placed on the advances in the roll-to-roll imprint process which have enabled us to produce working transistor arrays.

21.4: Zinc Indium Oxide Thin-Film Transistors for Active-Matrix Display Backplane

We report on the development of low-temperature gate dielectric materials for zinc indium oxide (ZIO) thin-film transistors (TFTs). Several films, including ALD HfO2 and PECVD SiNx (deposited at 175°C and 150°C, respectively), yield good TFT performance. Bias stress-induced threshold shift for HfO2 is quite small, however does not follow conventional trends associated with hydrogenated amorphous Si (a-Si:H) TFTs; PECVD SiNx conversely, shows bias stress characteristics that conform reasonably to a model appropriate for a-Si:H devices.

23.4: Invited Paper: Active‐Matrix Backplanes Produced by Roll‐to‐Roll Self‐Aligned Imprint Lithography (SAIL)

Progress in the development of a fully roll-to-roll self-aligned imprint process for producing active matrix backplanes with submicron aligned features on flexible substrates is reported. High performance transistors, crossovers and addressable active matrix arrays have been designed and fabricated using imprint lithography. Such a process has the potential of significantly reducing the costs of large area displays. The progress, current status and remaining issues of this new fabrication technology are presented.

High-current-density thin-film silicon diodes grown at low temperature

High-performance thin-film silicon n–i–p diodes are fabricated at temperatures below 160°C using hot-wire chemical vapor deposition. The 0.01mm2 diodes have a forward current-density of near 1000A∕cm2 and a rectification ratio over 107 at ±2V. Use of microcrystalline silicon i and n layers results in higher current-density diodes than with amorphous silicon, primarily by lowering a barrier to carrier injection. A 30nm intrinsic Si buffer layer between the i and p layers is needed to reduce the reverse leakage current. Minimizing diode area increases forward current density by reducing the voltage drop across the external series resistances.