Wei Yip Loh

Impact of interfacial layer control using Gd2O3 in HfO2 gate dielectric on GaAs

Structural and electrical properties of HfO2 and HfO2∕Gd2O3 gate stacks on p-GaAs substrates have been investigated. It has been demonstrated that the presence of thin layer of Gd2O3 between HfO2 and GaAs improves metal-oxide-semiconductor device characteristics such as interface state density, accumulation capacitance, frequency dispersion, and leakage current. It is also found that HfO2∕Gd2O3 stack can reduce the interfacial GaAs-oxide formation, thus reduce the outdiffusion of elemental Ga and As during post-thermal annealing process. Such suppression of outdiffusion significantly improves the electrical properties of the dielectric stacks.

Wide

For the first time, we demonstrate experimentally that by using HfLaO high-kappa gate dielectric, the flat-band voltage (Vfb) and the threshold voltage (Vth) of metal-electrode-gated MOS devices can be tuned effectively in a wide range (wider than that from the Si-conduction band edge to the Si-valence band edge) after a 1000-degC annealing required by a conventional CMOS source/drain activation process. As prototype examples shown in this letter, TaN gate with effective work function Phim,eff~3.9-4.2 eV and Pt gate with Phim,eff~5.5 eV are reported. A specific model based on the interfacial dipole between the metal gate and the HfLaO is proposed to interpret the results. This provides an additionally practical guideline for choosing the appropriate gate stacks and dielectric to meet the requirements of future CMOS devices

V_{\rm fb}

Using the carrier separation measurement technique, we are able to distinguish two different breakdown mechanisms: a high-k bulk initiated, and an interfacial layer initiated. The results correlate with the statistical Weibull distribution showing a polarity dependent breakdown in high-k stacks. A model of charge trapping at different spatial locations in HfAlO/sub x/ with a TaN gate structure is proposed to explain the polarity dependence of charge trapping characteristics and breakdown mechanisms.

and

A GaAs defect-free epitaxial layer has been grown on Si via a Ge concentration graded SiGe on insulator (SGOI) for application in high channel-mobility metal-oxide-semiconductor field effect transistor. The SGOI layer, 42nm thick, serves as the compliant and intermediate buffer to reduce the lattice and thermal expansion mismatches between Si and GaAs. A modified two-step Ge condensation technique achieves the surface Ge concentration in SGOI as high as 71%. It is also found that low-temperature migration enhanced epitaxy during the initial GaAs nucleation on the SGOI surface is critical to obtain a device quality GaAs layer by epitaxial growth.

V_{\rm th}

The effect of high nitrogen concentration incorporation using decoupled plasma nitridation (DPN) of ultra-thin gate oxide (≈15–17 A) on p-channel MOSFET performance has been investigated and compared with the conventional thermal nitridation process. Boron penetration is successfully suppressed in the ultra-thin gate dielectric prepared by the DPN process. This is confirmed by the measurements of gate leakage current, flat-band voltage shift and interface trap densities. The success in blocking boron penetration by DPN is attributed to its capability in incorporating a high level of nitrogen to near the top interface of the gate oxide. However, as a result of high level nitridation by DPN, a degradation in transconductance (Gm) is observed and interface trap density is also increased, compared to the conventional thermal nitridation process.

Tunability for Metal-Gated MOS Devices With HfLaO Gate Dielectrics

Our experiment shows that when the gate oxide thickness is scaled to direct tunneling regime, the gate leakage current, and the number of interface traps increase in a discrete manner rather than in a gradual increment. A direct correlation between the increments of the gate leakage current and interface traps, irrespective of stressing polarity, is also observed. The discrete increase in gate current is due to degradation at localized spots rather than a uniform degradation over the entire gate area. The increment is also observed over a wide voltage range unlike interface-trap-assisted tunneling previously reported which occurs mainly near the flat-band voltage. A possible mechanism is proposed based on the observations.

Analysis of charge trapping and breakdown mechanism in high-k dielectrics with metal gate electrode using carrier separation

The mechanism for quasi-breakdown (QB) in thin gate oxides was studied using bipolar current stress and unipolar constant current stress. Continual bipolar current stressing on the gate oxide shows two distinct stages of QB—recoverable and unrecoverable QB. During the recoverable QB stage, the gate leakage current recovers to the stress-induced leakage current level upon application of a proper reverse bias. In contrast, no electrical recovery is observed within the unrecoverable QB stage. This stage is characterized by a higher gate leakage current than that of the recoverable QB stage and a very stable gate voltage during stressing. Carrier separation measurements further demonstrate that two different modes of conduction can occur during the recoverable QB stage. In the early stage, Fowler–Nordheim electron tunneling dominates the conduction mechanism although a small hole current is observed. With prolonged electrical stress, the hole direct tunnelingcurrent becomes dominant. Based on the aforementioned observations and the monitoring of the generation of oxide traps using the direct-current current–voltage technique, a QB model of positive hole trapping at the anode is proposed.

Integration of GaAs epitaxial layer to Si-based substrate using Ge condensation and low-temperature migration enhanced epitaxy techniques

Dual metal gate integration scheme of using substituted Al (SA) and Pt/sub x/Si with high Pt concentration on high-K dielectric is proposed. The process can achieve a wide range of work function difference (0.65 eV) and is almost free from Fermi level pinning, without adverse effects of polysilicon predoping.

Impact of decoupled plasma nitridation of ultra-thin gate oxide on the performance of p-channel MOSFETs

Conventional oxide reliability studies determine oxide lifetime by measuring the time to breakdown or quasi-breakdown (QB). In ultrathin gate oxides with T/sub ox/<14 /spl Aring/, however, it is hard to observe breakdown or QB under typical stress conditions. Instead, the gate leakage current shows a continuous increase over the entire time period of electrical stress. As the magnitude of the gate current density increase eventually becomes too high to be acceptable for normal device operation, a lifetime criterion based on the increase in gate leakage current is proposed. Our paper also shows that the area-dependence of the gate leakage current density increase in 13.4 /spl Aring/ oxides is different from that in thicker oxide films, indicating a localized and discrete property of the leakage current. It has also been observed that the oxide lifetime based on the new lifetime criterion is shorter when the gate area is smaller, as opposed to the conventional area dependence of time-to-breakdown test. A simple model consisting of multiple degraded spots is proposed and it has been shown that localized gate leakage current can be described by Weibulls statistics for multiple degraded spots.

Correlation between interface traps and gate oxide leakage current in the direct tunneling regime

High performance Schottky Barrier Transistors (SBTs) have been demonstrated with Dopant Segregated (DS) Schottky source/drain [1]-[3]. DS-SBTs are demonstrated to have lower contact resistivity, better subthreshold behavior, higher on-state drive current and lower off-state leakage current. In addition, dopant segregation makes Schottky barriers tunable [1]. In this work, we introduce a strained Si/SiGe channel coupled with a low dosage of Dopant Segregated SB source/drain. The compressively strained SiGe epi-layer results in hole mobility enhancement and significant reduction in its hole Schottky barrier due to the narrow SiGe bandgap. Comparisons between Ni-silicided S/D and Pt-silicided S/D were also demonstrated. Hole Schottky barrier comparisons between Pt and Ni DS-SBTs with varying [Ge] concentrations in SiGe channel is also demonstrated.