Chew-Hoe Ang

Suppression of nitridation-induced interface traps and hole mobility degradation by nitrogen plasma nitridation

The impact of nitrogen plasma nitridation on the interfacial quality of ultrathin oxides (1.8 and 2.6 nm) have been investigated and compared with NO nitridation. It is found that plasma-nitrided oxides are more immune tonitridation-induced degradation of channel hole mobility, and have lower intrinsic interlace-trap density as compared to NO-nitrided oxides. In addition, plasma-nitrided oxides can further suppress hole mobility degradation induced by boron penetration. The superior performance of nitrogen plasma nitridation is attributed to its capability of incorporating a high level of nitrogen at the top oxide surface, while keeping the Si-SiO 2 interface intact.

Bias and thermal annealings of radiation-induced leakage currents in thin-gate oxides

The effects of bias annealing and thermal annealing on radiation-induced leakage currents (RILC) in thin-gate oxides (4.5 nm) have been studied. To decouple these two effects, we have performed the bias annealing at room temperature and the thermal annealing at elevated temperatures without bias. RILC has been found to decrease after both bias and thermal annealings. We have also observed that the decrease of RILC during bias annealing was greatly enhanced in a hydrogen ambient. This evidence strongly indicates that trapped holes contribute significantly to RILC and suggests that the bias annealing of RILC was likely due to the annealing of trapped holes.

A comparative study of radiation- and stress-induced leakage currents in thin gate oxides

Low-field leakage currents in thin gate oxides can be induced by 10 keV x-ray irradiation and electrical stress. The characteristics of radiation-induced leakage current (RILC) and stress-induced leakage current (SILC) in thin oxides have been studied and compared. The characteristics of RILC are found to be very similar to SILC, indicating that both RILC and SILC have essentially the same conduction mechanism, and are contributed by common defects generated in the gate oxides during irradiation or electrical stress. In particular, it has been demonstrated that oxide-trapped holes contribute significantly to both RILC and SILC.

Characterization of interface degradation in deep submicron MOSFETs by gate-controlled-diode measurement

Abstract The gate-controlled-diode (GCD) characteristic of a deep submicron MOSFET is changed dramatically following a Fowler–Nordheim (FN) injection. The changes can be explained by the trap generation on the Si surface close to the channel/drain edge and the interface trap generation in the channel region. By examining the change in the reverse drain current under accumulation and inversion in the GCD measurements, the information of trap generation in the surface region close to the channel/drain edge is obtained (note that the trap generation in this region could be different from that in other interface regions); and by measuring the reverse drain current under depletion, the interface trap generation in the channel region is obtained.

Influence of interfacial nitrogen on edge charge trapping at the interface of gate oxide/drain extension in metal-oxide-semiconductor transistors

In this work, the edge charge trapping at the interface of gate oxide/drain extension caused by Fowler–Nordheim injection is determined quantitatively by using a simple approach to analyze the change of the drain band-to-band tunneling current. For both pure and nitrided oxides with an oxide thickness of 6.5 nm, positive edge charge trapping is observed while the net charge trapping in the oxide above the channel is negative. It is found that the nitrogen at the interface can enhance the edge charge trapping. The results could be explained in terms of the creation of positive fixed oxide charges at the interface as a result of the electrochemical reactions involving holes and hydrogen ions.

A quantitative study of the relationship between the oxide charge trapping over the drain extension and the off-state drain leakage current

In this letter, we report an approach to quantitative study of the relationship between the oxide charge trapping over the drain extension due to electrical stress and the off-state drain leakage current. It is found that positive charge trapping over the drain extension leads to a significant increase in the off-state drain current if the edge direct tunneling (EDT) is dominant in the drain current but in contrast, it leads to a reduction in the drain current if the band-to-band tunneling in the Si surface is dominant. A quantitative relationship between the charge trapping and the off-state drain leakage current in the EDT regime is established. From the measurement of the off-state current in the EDT regime, the charge trapping can be determined by using the approach developed in this study.

Power-Law Dependence of Charge Trapping on Injected Charge in Very Thin SiO2 Films

In this letter, we report a novel approach to quantitative determination of charge trapping in gate oxide caused by high field stress. Our approach is to analyze the small but significant change in the post-stress FN tunneling current through the oxide layer based on the assumption that the change in the tunneling current is due to the changes of both the oxide field and the oxide barrier heights caused by charge trapping in the oxide and at the interfaces. It is found that, regardless of injection directions and measurement polarities, the charge trapping always follows a power law of the form Qinjn with n≈0.1 to 0.4, where Qinj is the injected charge dose.

The impact of post-polysilicon gate process on ultra-thin gate oxide integrity

Abstract The impact of rapid-thermal spike anneal after source/drain extension (SDE) implant on the integrity of ultra-thin gate oxide is studied. It is found that SDE anneal can cause increasingly severe gate oxide integrity (GOI) degradation as the gate oxide becomes thinner. The GOI degradation can be suppressed by growing a thin oxide on the polysilicon gate or inserting an offset spacer prior to the SDE implant step. Additionally, a close correspondence between GOI degradation, gate to source/drain leakage current, and the bridging of dense polysilicon lines is observed, indicating a common origin for these phenomena.

Impacts of Buffer Oxide Layer in Nitride/Oxide Stack Gate Dielectrics on the Device Performance and Dielectric Reliability

The device performance and reliability of nitride/oxide stack gate dielectrics with different buffer oxide thickness has been studied. The stack dielectrics were fabricated by in situ H (2%)/O 2 anneal of chemical vapor deposited Si 3 N 4 . Ellipsometry data indicates the formation of SiO 2 at the Si 3 N 4 /Si interface. With decreasing thickness of the buffer oxide, the gate leakage current reduced while the reliability and metal oxide semiconductor field effect transistor performance were degraded. The degradation in the reliability is attributed to the extension of structural strained layer into the Si 3 N 4 bulk. Our results suggest that a buffer oxide of ∼10 A is needed for the implementation of Si 3 N 4 gate dielectric for future high performance complementary metal oxide semiconductor devices.

Annealing of Fowler‐Nordheim Stress‐Induced Leakage Currents in Thin Silicon Dioxide Films

The mechanism and characteristics of bias annealing of Fowler-Nordheim stress-induced leakage currents (SILC) in thin silicon dioxide films (4.5 nm) at room temperature have been investigated. It is shown that the degree of SILC reduction increases with the anneal gate bias, irrespective of the polarity of the anneal bias. Furthermore, the bias annealing of SILC is found to be greatly enhanced in a hydrogen ambient, thus providing a strong physical evidence that trapped holes are contributing significantly to SILC. The result also suggests that the mechanism of bias annealing is likely related to the annealing of trapped holes. In addition, unbiased thermal annealing of SILC has been studied and compared to the bias annealing. A portion of the SILC apparently annealed out by bias annealing can be reactivated, while thermal annealing causes a permanent annihilation of SILC.