Wen-Fa Wu

Schottky Barrier Silicon Nanowire SONOS Memory With Ultralow Programming and Erasing Voltages

A new Schottky barrier (SB) nonvolatile nanowire memory is reported experimentally with efficient low-voltage programming and erasing. By applying an SB source/drain to enhance the electrical field in the silicon gate-all-around nanowire, the nonvolatile silicon-oxide-nitride-oxide-silicon (SONOS) memory can operate at gate voltages of 5 to 7 V for programming and -7 to -9 V for erasing through Fowler-Nordheim tunneling. The larger the gate voltage is, the faster the programming/erasing speed and the wider the threshold-voltage shift are attained. Importantly, the SB nanowire SONOS cells exhibit superior 100-K cycling endurance and high-temperature retention without any damages from metallic silicidation process or field-enhanced tunneling.

Multilevel Schottky Barrier Nanowire SONOS Memory With Ambipolar n- and p-Channel Cells

A novel multilevel Schottky barrier nonvolatile nanowire memory is experimentally reported with low-voltage operations and excellent reliability. Using efficient hot-electrons and hot-holes generation associated with Schottky barrier source/drain, the multilevel schemes of silicon nanowire silicon-oxide-nitride-oxide-silicon (SONOS) cells are achieved at adequately low gate voltages. The n-channel cells work at a small gate voltage of 5 to 7 V using multilevel electron programming, whereas the p-channel cells operate at a low gate voltage of -7 to -11 V using multilevel hole programming. The roles of electron and hole carriers in the n-channel cells are exchanged in the p-channel nanowire cells because of ambipolar conduction. Both the n- and p-channel multilevel Schottky barrier nanowire SONOS cells preserve excellent thermal retention and cycling endurance for use in practical embedded and stand-alone nonvolatile memories.

Dopant segregated Schottky barrier nanowire transistors using low-temperature microwave annealed ytterbium silicide

Thermal budget is one of the major concerns to fabricate three-dimensional (3D) transistors using practical CMOS technologies. In this work, low-temperature microwave annealing is utilized for the fabrication of dopant segregated Schottky barrier gate-all-around nanowire transistors. Low electron Schottky barrier of ytterbium silicide was combined with Phosphorus segregation to form metallic source/drain for high-performance N-channel nanowire transistors. Effects of microwave annealing on metal silicidation as well as dopants segregation are intensively examined by comparing with those using rapid thermal annealing. The minimum microwave power of 200% and processing time of 200 s can be used during annealing to minimize the thermal energy while retaining sufficient activation and silicidation. Experimental results show that the microwave annealing produce better electrical characteristics of dopant segregated Schottky barrier nanowire transistors, serving as a promising approach to fabricate metallic source/drain nanowire transistors for future 3D integration of CMOS technologies.

Impact of Edge Encroachment on Programming and Erasing Gate Current in nand -Type Flash Memory

The edge encroachment of tunnel oxide is experimentally found to degrade the Fowler-Nordheim (FN) tunneling gate current of NAND-type Flash cells. This work elucidates the impact of edge encroachment on FN tunneling current for use in programming and erasing operations. The fringing field effect and tunnel oxide with trapezoidal edge are considered in the determination of physical gate current in which a conformal-mapping method is used to estimate the contribution of the fringing fields. These analytical results are confirmed using 2-D device simulations and experimental measurements. The results show that the overlapped encroachment causes an exponential degradation of intrinsic FN tunneling current. Preventing the encroachment of lateral edges resulting from overall tunnel-oxide enlargement is critical to ensuring normal programming and erasing speeds in future NAND-type Flash cells.

Drain-induced Schottky barrier source-side hot carriers and its application to program local bits of nanowire charge-trapping memories

A new mechanism of drain-induced Schottky barrier lowering is reported experimentally for Schottky barrier nanowire devices. The strong drain-induced barrier lowering and associated source-side hot electrons were employed to program the localized bits of nanowire charge-trapping memory cells. For Schottky barrier nanowire devices, two different mechanisms of Schottky barrier lowering are classified: 1) gate-controlled and 2) drain-induced. In the drain-mode conduction, the lowering of Schottky source barrier relies on the drain voltage. The smaller gate voltage and the larger drain voltage are, the higher drain current is attained. The pure drain-induced current can locally program the nanowire charge-trapping cells at a drain voltage of 5–6 V. The decoupled forward and reverse reading curves confirm the trap charges are sorely programmed at the source-side region. This new drain-induced lowering mechanism provides a practical approach to program the multi-bit/cell NOR-type nanowire charge-trapping memories, and the drain-mode programming preserves excellent thermal retention and cycling endurance.

A Localized Two-Bit/Cell Nanowire SONOS Memory Using Schottky Barrier Source-Side Injected Programming

A localized two-bit/cell silicon nanowire silicon-oxide-nitride-oxide-silicon memory is experimentally presented for the use in future multibit/cell or NOR Flash applications. Instead of conventional channel-hot-electron programming used in charge-trapping cells, the localized charge storages are performed using the Schottky barrier source-side electron programming. The selection of applying a drain or source voltage determines the injected location of storage bits during cell programming. The locally trapped charges decouple the conduction of electron current from the ambipolar hole current to generate an enlarged sensing window. The results of reliability and characterization tests confirm the localized storage cells preserve excellent low voltage, operation speed, cycling endurance, and thermal retention as the nonlocalized counterparts.

Sub-10V 4-bit/cell Schottky barrier nanowire nonvolatile memory

This study reports experimentally a novel sub-10V 4-bit/cell nanowire silicon-oxide-nitride-oxide-silicon (SONOS) memory cell for use in nonvolatile NAND Flash memories. Applying metallic Schottky barrier source/drain in the silicon gate-all-around nanowire SONOS cells enables the multi-level 4-bit/cell SONOS memory to operate at sub-10V gate voltages using efficient electron programming and hole erasing through Fowler-Nordheim mode tunneling. Examples of 2-bit/cell, 3-bit/cell, and 4-bit/cell applications in this Schottky barrier nanowire SONOS memory cell are demonstrated with multi-level electron programming. Reliability characterization confirms these multi-bit cells to operate well after 10K cycling endurance and 125°C high temperature retention stress.

Formation of arsenic segregated Ytterbium and Nickel silicide using microwave annealing

This work investigates the formation of arsenic segregated Ytterbium and Nickel silicide using low-temperature microwave annealing. Two types of dopant segregation approaches, implant-before-silicidation and implantation-through-metal, are performed to examine the electrical properties of the microwave annealed silicide. Results of current-voltage curves and dopant distribution profiles are compared with those using rapid thermal annealing.

P-channel Schottky barrier nanowire SONOS memory with low-voltage operations and excellent reliability

An ultralow voltage p-channel Schottky barrier nanowire SONOS memory is reported experimentally with excellent reliability. By applying pure metallic Schottky barrier S/D, the nanowire SONOS memory can operate at a gate voltage of -7V to -11V for hole programming, and 5V to 7V for electron erasing. This Schottky barrier cell exhibits superior 10K cycling and 125°C retention for practical applications.

Efficient and reliable Schottky barrier silicon nanowire charge-trapping flash memory

This paper presents experimentally a novel Schottky barrier (SB) silicon nanowire charge-trapping memory with low-voltage operations and excellent reliability. The unique SB source/drain junctions are utilized to produce strong enhancements of hot-electrons or hot-holes generations to perform efficient programming and erasing (P/E). The efficient P/E injections enable the multi-level SB memory cells to operate at sub-10V gate voltages through Fowler-Nordheim mode P/E. Additionally, the roles of electron and hole carriers in N-channel cells can be switched directly to operate the SB nanowire devices in P-channel cells because of ambipolar conduction. Reliability characterization confirms the SB nanowire cells operate well after cycling endurance and data retention tests.