Wen-Hsien Tu

Nearly defect-free Ge gate-all-around FETs on Si substrates

The p-channel triangular Ge gate-all-around (GAA) FET with fin width (W<inf>fin</inf>) of 52nm and L<inf>g</inf> of 183nm has I<inf>on</inf>/I<inf>off</inf> =10⁵, SS= 130mV/dec, and I<inf>on</inf>=235 µA/µm at −1V. Performance can be further improved if superior gate stack than EOT=5.5 nm and D<inf>it</inf>=2×10¹² cm⁻²eV⁻¹ is used. A novel process to etch away the high defect Ge near Ge/Si interface from blanket Ge grown on SOI can solve the loading effect in the selective growth, achieve better gate control by GAA with larger effective width (W<inf>eff</inf>) than rectangular fin, and have low punch-through current through the Si substrate due to the oxide under the Ge channel and the valence band discontinuity at the Ge S/D and Si interface. By dislocation removal, the defect-free Ge channel can be formed on nothing.

Ferroelectric negative capacitance hetero-tunnel field-effect-transistors with internal voltage amplification

The ferroelectric negative capacitance (NC) hetero-tunnel FET is fabricated for the first time, demonstrating the significant improvement in subthreshold swing (~double slope) and peak gm (118% enhancement) due to the internal voltage amplification. The peak gm enhancement at small VDS (-0.1V) indicates the intrinsic benefit by NC without lateral bias. The concept of coupling the ferroelectric polarization is proposed and synergistically contributes to the performance in future applications of steep subthreshold slope devices.

Triangular-channel Ge NFETs on Si with (111) sidewall-enhanced I on and nearly defect-free channels

Due to the highest electron mobility (2200 cm²/Vs) on (111) Ge surface, the n-channel triangular Ge gate-all-around (GAA) FET with (111) sidewalls on Si and L_g=350 nm shows 2x enhanced I_on of 110 μA/μm at 1V with respect to the devices with near (110) sidewalls. A novel process to etch away the defective Ge near Ge/Si interface from epitaxial Ge grown on SOI achieves a nearly defect-free channel, good gate control triangular gate, and larger effective width. Electrostatic control of SS= 94 mV/dec (at 1V) can be further improved if superior gate stack than EOT= 5.5 nm and D_it= 1×10¹² cm^-2eV^-1 is used. The I_on can be further enhanced if the line edge roughness (LER) can be reduced. The Ge GAA n-FET is reported for the first time with CMOS compatible process, which makes the circuits integration much easier.

Junctionless Gate-All-Around pFETs Using In-situ Boron-Doped Ge Channel on Si

Junctionless devices exhibit favorable I_on/I_off and SS in high-mobility Ge channels owing to the elimination of junction leakage. With channel doping of 5 × 10¹⁸ cm^-3, the fin width of 27 nm and the gate length of 250 nm, our gate-all-around device has the I_on/I_off of 1 × 10⁶, the SS of 95 mV/dec, and the I_on of 275 μA/μm. The drain current reaches 390 μA/μm for the device with channel doping of 8 × 10¹⁹ cm^-3, and the fin width of 9 nm. The junctionless devices show higher mobility in the large V_GS-V_T region than the inversion mode devices due to less dependence on surface roughness scattering. Junctionless devices also show increasing drive current at increasing temperatures due to the nature of impurity scattering.

Ferroelectric gate tunnel field-effect transistors with low-power steep turn-on

Using a ferroelectric PbZrTiO3 gate stack, the range of the steep subthreshold swing in tunnel field-effect transistors was extended by 3.5 orders of magnitude demonstrating an improvement in the swing (by approximately double the slope). The drain conductance (gd) shows only 16% enhancement with large V DS (∼−1.5V) indicates internal voltage amplification with ferroelectric negative capacitance effect beneficial to small lateral drain-source bias voltages (−0.1 V). The concept of coupling the ferroelectric polarization is proposed. The power consumption is also discussed in low-power applications of steep subthreshold slope devices.

The pn Junctions of Epitaxial Germanium on Silicon by Solid Phase Doping

Boron and phosphorous layers were deposited by ultrahigh-vacuum chemical vapor deposition at 450 °C using B₂H₆ and PH₃, respectively, to form the abrupt doping profiles in epitaxial Ge on Si substrate. The diffusion process without ion implantation damage is demonstrated by the nearly ideal diode characteristics for the first time. The Ge diodes doped by the boron layer and the phosphorous layer have the ON/OFF ratio of ~1×10⁵ and ~1.5×10⁵ with the extremely low reverse current densities of ~1×10^-4 A/cm² and ~4 × 10^-5 A/cm², respectively. The good crystalline quality at junction free from implantation damage by in situ solid phase doping reflects these figures of merit.

In-situ doped and tensily stained ge junctionless gate-all-around nFETs on SOI featuring I on = 828 µA/µm, I on /I off ∼ 1×10 5 , DIBL= 16–54 mV/V, and 1.4X external strain enhancement

In-situ CVD doping and laser anneal can reach [P] and tensile strain as high as 2×10²⁰ cm^-3 and 0.34%, respectively, in Ge on SOI with low defect density and high activation rate (nearly 100% near the surface), and enables high performance of the junctionless (JL) Ge gate-all-around (GAA) nFETs. The device with the W_fin of 13 nm, EOT of 10 nm, and nominal L_G of 280 nm has I_on = 350 μA/μm, I_on/I_off = 3×10⁶, SS = 185 mV/dec, and DIBL = 16 mV/V. The device with the W_fin of 9 nm and EOT of ~ 0.8 nm achieves the record high I_on of 828 μA/μm at V_GS - V_T = 1.5 V and V_DS = 2 V with DIBL = 54 mV/V, I_on/I_off = 1×10⁵ and SS = 150 mV/dec. Besides the epitaxial tensile strain (0.34%) generated by laser anneal due to the misfit of thermal expansion coefficients between Ge and Si, the enhanced tensile strain by the microbridge structure is also beneficial for I_on. The drain current enhancement of ~40% is achieved under the mechanical uniaxial tensile strain of ~0.25% due to sub-band splitting and carrier repopulation into the L4 valleys with the small conductive effective mass. The non-uniform shape of Ge channel with a minimum width at the center leads to enhanced I_on as compared to uniform channel. The extracted mobility of JL devices increases with increasing temperature, indicating the domination of impurity scattering. The threshold voltage of JL devices has the negative temperature coefficient and EOT scaling reduces the temperature dependence.

A transition of three to two dimensional Si growth on Ge (100) substrate

For the initial growth of Si on Ge, three-dimensional Si quantum dots grown on the Ge surface were observed. With increasing Si thickness, the Si growth changes from three-dimensional to two-dimensional growth mode and the dots disappear gradually. Finally, the surface is smooth with the roughness of 0.26 nm, similar to the original Ge substrate, when 15 nm Si is deposited. More Ge segregation on the wetting layer leads to more open sites to increase the subsequent Si growth rate on the wetting layer than on the Si dots. The in-plane x-ray diffraction by synchrotron radiation is used to observe the evolution of tensile strain in the Si layer grown on Ge (100) substrate.

Junctionless Gate-all-around pFETs on Si with In-situ doped Ge channel

High performance junctionless Ge Gate-all-around pFETs with fin width down to 9 nm are demonstrated. The device with the L_eff of 250 nm and channel doping of 8×10 cm- has I_on/I_off= 1×10, SS = 95 mV/dec, and I_on = 390 μA/μm. The gate controllability can be further improved with low EOT gate stack of ~ 0.7 nm for the SS down to 84 mV/dec. Junctionless devices also show higher mobility at the large V_Gs - V_t region than the inversion mode devices due to less dependence on surface roughness scattering. The configuration of fin width and channel concentration to achieve low SS is investigated.

Ge gate-all-around FETs on Si

High performance Ge inversion (INV) and junctionless (JL) gate-all-around (GAA) FETs are demonstrated on epi-Ge layer on SOI. The anisotropic etching is used to remove the defect near the Ge/Si interface and to form gate-all-around structure. The INV and JL pGAAFETs have I_on of 235 μA/μm and 270 μA/μm at V_GS - V_T = -2 V and V_DS = -1 V, respectively, and show good subthreshold characteristics. The (111) sidewall INV nFETs show 2X enhanced I_on of 110 μA/μm with respect to the devices with near (110) sidewalls.