Guang-Li Luo

Competitiveness between direct and indirect radiative transitions of Ge

Both direct and indirect transitions of photoluminescence and electroluminescence are observed in a Ge n+p diode. The relative intensity of direct radiative recombination with respect to indirect radiative recombination increases with the increase in the optical pumping power, injection current density, and temperature. The increase in electron population in the direct valley is responsible for the enhancement. The spectra can be fitted by the combination of direct and indirect transition models. The direct radiative transition rate is ∼1600 times of the indirect transition, estimated by electroluminescence and photoluminescence spectra near room temperature.

Characteristics of Atomic-Layer-Deposited Al2O3 High-k Dielectric Films Grown on Ge Substrates

This paper describes the structural and electrical properties of Al 2 O 3 thin films grown through atomic layer deposition onto Ge substrates over a wide deposition temperature range (50-300°C). From grazing-incidence X-ray reflectivity and X-ray photoelectron spectroscopy, we found that increasing the deposition temperature improved the Al 2 O 3 film density and its dielectric stoichiometry; nevertheless, dielectric intermixing between main Al 2 O 3 and interfacial GeO 2 appeared at temperatures above 200°C, along with degradation of the GeO 2 /Ge interface. Accordingly, a relatively large gate leakage current (J g ) and a high density of interfacial states D it (>10 13 cm -2 eV -1 ) were observed as a result of deterioration of the entire Al 2 O 3 /Ge structure at higher deposition temperatures. In addition, although subsequent high-temperature processing at 600°C in a N 2 ambient could relieve the oxygen-excessive behavior further, i.e., to provide a more stoichiometric film, the accompanying GeO x volatilization close to the dielectric interface caused greater damage to the electrical performance. Only forming gas annealing (H 2 /N 2 , 1:10) at low temperature (300°C) improved the capacitance-voltage characteristics of the Pt/Al 2 O 3 /Ge structure, in terms of providing a lower value of D it (ca. 6 X 10 11 cm -2 eV -1 ), a lower value of J g , and a reduced hysteresis width.

Growth of high-quality Ge epitaxial layers on Si(100)

A method of growing high-quality epitaxial Ge layers on a Si(100) substrate is reported. In this method, a 0.8 mum Si0.1Ge0.9 layer was first grown. Due to the large lattice mismatch between this layer and the Si substrate, many dislocations form near the interface and in the lower part of the Si0.1Ge0.9 layer. A 0.8 mum Si0.05Ge0.95 layer and a 1.0 mum top Ge layer were subsequently grown on the Si0.1Ge0.9 layer. The formed interfaces of Si0.05Ge0.95/Si0.1Ge0.9 and Ge/Si0.05Ge0.95 can bend and terminate the upward-propagated dislocations very effectively. The in situ annealing process was also performed for each individual layer. Experimental results show that the dislocation density in the top Ge layer can be greatly reduced, and the surface is very smooth, while the total thickness of the structure is only 2.6 mum. (Less)

High quality Ge thin film grown by ultrahigh vacuum chemical vapor deposition on GaAs substrate

High-quality epitaxial Ge films were grown on GaAs substrates by ultrahigh vacuum chemical vapor deposition. High crystallinity and smooth surface were observed for these films by x-ray diffraction, transmission electron microscopy, and atomic force microscopy. Direct band gap emission (1550 nm) from this structure was detected by photoluminescence. Valence band offset of 0.16 eV at the Ge/GaAs interface was measured by x-ray photoelectron spectroscopy. N-type arsenic self-doping of 1018/cm−3 in the grown Ge layers was determined using electrochemical capacitance voltage measurement. This structure can be used to fabricate p-channel metal-oxide-semiconductor field-effect transistor for the integration of Ge p-channel device with GaAs n-channel electronic device.

High-speed GaAs metal gate semiconductor field effect transistor structure grown on a composite Ge∕GexSi1−x∕Si substrate

In this study we used a low-pressure metal organic vapor phase epitaxy method to investigate the growth of GaAs metal gate semiconductor field effect transistor (MESFET) structures on a Si substrate. The buffer layer between the Si substrate and the grown GaAs epitaxial layers was a composite Ge∕Si0.05Ge0.95∕Si0.1Ge0.9 metamorphic layer. We used transmission electron microscopy to observe the microstructures formed in the grown GaAs∕Ge∕SixGe1−x∕Si material and atomic force microscopy to analyze the surface morphology and the formation of antiphase domains in the GaAs epitaxial layers. The measured Hall electron mobility in the channel layer of a MESFET structure grown on a 6° misoriented Si substrate was 2015 cm2 V−1 s−1 with a carrier concentration of 5.0×1017 cm−3. The MESFET device fabricated on this sample exhibited good current-voltage characteristics.

Nearly defect-free Ge gate-all-around FETs on Si substrates

The p-channel triangular Ge gate-all-around (GAA) FET with fin width (W<inf>fin</inf>) of 52nm and L<inf>g</inf> of 183nm has I<inf>on</inf>/I<inf>off</inf> =10⁵, SS= 130mV/dec, and I<inf>on</inf>=235 µA/µm at −1V. Performance can be further improved if superior gate stack than EOT=5.5 nm and D<inf>it</inf>=2×10¹² cm⁻²eV⁻¹ is used. A novel process to etch away the high defect Ge near Ge/Si interface from blanket Ge grown on SOI can solve the loading effect in the selective growth, achieve better gate control by GAA with larger effective width (W<inf>eff</inf>) than rectangular fin, and have low punch-through current through the Si substrate due to the oxide under the Ge channel and the valence band discontinuity at the Ge S/D and Si interface. By dislocation removal, the defect-free Ge channel can be formed on nothing.

A Low-Temperature Microwave Anneal Process for Boron-Doped Ultrathin Ge Epilayer on Si Substrate

High source/drain concentration level, ultrashallow junction, and high-mobility channel are important for the requirements of nanoscale transistors. Microwave processing of semiconductors could offer distinct advantages over conventional RTP systems in some applications, and the anneal temperature is within the range of 300degC-500degC. By using a low-temperature microwave anneal, the sheet resistance and boron diffusion in the Si/Ge/Si substrate could be reduced effectively, and the crystalline structure of Si/Ge/Si is not damaged according to the TEM image and the XRD signals.

Study of the Erase Mechanism of MANOS (

The erase characteristics and mechanism of metal- Al2O3-nitride-oxide-silicon (MANOS) devices are extensively studied. We use transient analysis to transform the erase curve (VFB - time) into a J-E curve (J = transient current, E = field in the tunnel oxide) in order to understand the underlying physics. The measured erase current of MANOS is three orders of magnitude higher than that can be theoretically provided by substrate hole current. In addition, the erase current is very sensitive to the Al2O3 processing condition - also inconsistent with substrate hole injection model. Thus, we propose that MANOS erase occurs through an electron detrapping mechanism. We have further carried out a refill test and its results support the detrapping model. Our results suggest that the interfacial layer between Al2O3 and nitride is a key process that dominates the erase mechanism of MANOS.

\hbox{Metal/Al}_{2}\hbox{O}_{3}/\hbox{SiN/SiO}_{2}/\hbox{Si}

The record high peak mobility of ∼1050 cm²/V-s on (001) Ge substrate is demonstrated in NFET. High-quality Ge/GeO<inf>2</inf> interface is ensured by rapid thermal oxidation (RTO) and remote ozone plasma treatment. The best achieved subthreshold swing is 150mV/dec and the on/off ratio is 2×10⁴. The low defective n⁺/p junction produced a record high on/off ratio of 2×10⁵, an ideality factor of 1.05 and strong electroluminescence. For the first time, it is reported that the uniaxial &#60;110> tensile strain (0.08%) on &#60;110> channel direction gives the best mobility enhancement (12%) among the different strain configurations, consistent with theoretical calculation.

) Device

In this letter, high-performance p-channel polycrystalline-silicon thin-film transistors (TFTs) using hafnium- silicate (HfSiO_x) gate dielectric are demonstrated with low- temperature processing. Because of the higher gate-capacitance density, TFTs with HfSiO_x gate dielectric exhibit excellent device performance in terms of higher I_ON/I_OFF current ratio, lower subthreshold swing, and lower threshold voltage (V_th) albeit with slightly higher OFF-state current. More importantly, the mobility of TFTs with HfSiO_x gate dielectric is 1.7 times that of TFTs with conventional deposited-SiO₂ gate dielectric.