Wen-Luh Yang

SONOS-type flash memory using an HfO/sub 2/ as a charge trapping layer deposited by the sol-gel spin-coating method

In this letter, the authors fabricate the silicon-oxide-nitride-oxide-silicon (SONOS)-like memory using an HfO2 as charge trapping layer deposited by a very simple sol-gel spin-coating method and 900 degC 1-min rapid thermal annealing. They examine the quality of sol-gel HfO2 charge trapping layer by X-ray photoemission spectroscopy, Id-Vg, charge retention, and endurance. The threshold voltage shift is 1.2 V for the sol-gel HfO2 trapping layer. The sol-gel HfO2 film can form a deep trap layer to trap electrons for the SONOS-like memory. Therefore, the sol-gel device exhibits the long charge retention time and good endurance performance. The charge retention time is 104 s with only 6% charge loss and long endurance program/erase cycles up to 105

Highly Reliable Multilevel and 2-bit/cell Operation of Wrapped Select Gate (WSG) SONOS Memory

In this letter, high-performance and reliable wrapped select gate (WSG) polysilicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multilevel and 2-bit/cell operation have been successfully demonstrated. The multilevel storage is easily obtained with fast program/erase speed (10 mus/5 ms) and low programming current (3.5 muA) for our WSG SONOS by a source-side injection. Besides the excellent reliability properties of our multilevel WSG-SONOS memory including unconsidered gate and drain disturbance, long charge retention (>150degC) and good endurance (>104) are also presented. This novel WSG-SONOS memory with a multilevel and 2-bit/cell operation can be used in future high-density and high-performance memory application

High-Program/Erase-Speed SONOS With In Situ Silicon Nanocrystals

In this letter, for the first time, we have successfully fabricated silicon-oxide-nitride-oxide-silicon (SONOS) devices with embedded silicon nanocrystals (Si-NCs) in silicon nitride using in situ method. This process is simple and compatible to modern IC processes. Different Si-NCs deposition times by in situ method were investigated at first. SONOS devices with embedded Si-NCs in silicon nitride exhibit excellent characteristics in terms of larger memory windows (> 5.5 V), lower operation voltage, high P/E speed, and longer retention time (> 108 s for 13% charge loss).

The Synergistic Effect of N 2 / H 2 Gases in the Plasma Passivation of Siloxane-Based Low-k Polymer Films

This work examines the impact of the chemistry of the gas mixture (N 2 /H 2 ) and the plasma-related operating conditions on etching and/or passivation of siloxane-based polymer (HOSP) films. Plasmas generated using an inadequate power source and an H 2 -dominating chemistry tend to induce the removal of carbonaceous species and over-cross-linking from such a films structure. sharply degrading the films dielectric constant (k) and insulating capacity. Nonetheless, properly adjusting the operating power supply and shifting the gas mixture toward the N 2 -dominant regime cause the N 2 /H 2 plasma to outperform the commonly used NH 3 and N 2 plasmas with respect to protecting the films against O 2 plasma damage, by forming a surface nitride layer.

Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals

In this paper, silicon-oxide-nitride-oxide-semiconductor (SONOS) devices with embedded silicon nanocrystals (Si-NCs) in silicon nitride using in situ method with multilevel and 2-b/cell operation have been successfully demonstrated. The proposed in situ Si-NC deposition method exhibits the advantages of low cost, simplicity, and compatibility with modern IC processes. SONOS memories with embedded Si-NCs exhibit a significantly improved performance with a large memory window (> 5.5 V), low operating voltage (P/E voltage: V_g = 6 V, V_d = 7 V and V_g = -7 V, V_d = 10 V, respectively), greater tolerable gate and drain disturbance (V_t shift <; 0.2 V), negligible second-bit effect, high P/E speed (after programming time = 10 μs with a 2-V shift of V_t under V_g = V_d = 6 V operation), good retention time (> 10⁸ s for 13% charge loss), and excellent endurance performance (after 10⁴ P/E cycles with a memory window of 3 V).

Novel Fabrication of Cu Interconnection by Displacing the Prepatterned Ti Film for ULSI

The process of fabricating Cu layers by displacement reaction is demonstrated. In our experiments, Ti was used and displaced in the chemical reaction process to form copper films. TiN was also adopted to improve adhesion between the copper and the dielectric layer. The effects of the process recipe on the structure and reliability of the Cu lines were studied. The obtained average electrical resistivity of the Cu films was 2.04 μΩ cm after thermal annealing and 2.18 μΩ cm for samples grown from a less-oxygen-containing solution. Study of the reliability showed that the activation energy of the copper interconnect was 0.92 eV, which is very close to the result for Cu films grown by sputtering.

SONOS memories with embedded silicon nanocrystals in nitride

In this work, we have successfully demonstrated SONOS memories with embedded Si-NCs in silicon nitride by in-situ deposition method. The self-assembly silicon nanocrystals were in-situ deposited within the Si3N4 storage layer by dissociation of dichlorosilane (SiH2Cl2) gas to a high density of 9 times 1011 cm-2. This new structure exhibits larger memory windows for up to 6 V, better program/erase characteristics, and excellent data retention properties as compared to control device. In addition, this novel process is simple, low cost, and compatible to the standard complementary metal-oxide-semiconductor (CMOS) processes. This technology seems to be very promising for the advanced flash memory devices.

Advanced Cu chemical displacement technique for SiO2-based electrochemical metallization ReRAM application

This study investigates an advanced copper (Cu) chemical displacement technique (CDT) with varying the chemical displacement time for fabricating Cu/SiO2-stacked resistive random-access memory (ReRAM). Compared with other Cu deposition methods, this CDT easily controls the interface of the Cu-insulator, the switching layer thickness, and the immunity of the Cu etching process, assisting the 1-transistor-1-ReRAM (1T-1R) structure and system-on-chip integration. The modulated shape of the Cu-SiO2 interface and the thickness of the SiO2 layer obtained by CDT-based Cu deposition on SiO2 were confirmed by scanning electron microscopy and atomic force microscopy. The CDT-fabricated Cu/SiO2-stacked ReRAM exhibited lower operation voltages and more stable data retention characteristics than the control Cu/SiO2-stacked sample. As the Cu CDT processing time increased, the forming and set voltages of the CDT-fabricated Cu/SiO2-stacked ReRAM decreased. Conversely, decreasing the processing time reduced the on-state current and reset voltage while increasing the endurance switching cycle time. Therefore, the switching characteristics were easily modulated by Cu CDT, yielding a high performance electrochemical metallization (ECM)-type ReRAM.

Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory

In this paper, highly reliable wrapped-select-gate (WSG) silicon–oxide–nitride–oxide–silicon (SONOS) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism for WSG-SONOS memory with different ONO thickness was thoroughly investigated. The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results. Furthermore, multi-level storage is easily obtained, and good VTH distribution presented, for the WSG-SONOS memory with optimized ONO thickness. High program/erase speed (10 µs/5 ms) and low programming current (3.5 µA) are used to achieve the multi-level operation with tolerable gate and drain disturbance, negligible second-bit effect, excellent data retention and good endurance performance.

Fabrication of SONOS-Type Flash Memory with the Binary High-k Dielectrics by the Sol-Gel Spin Coating Method

We fabricated the binary high-k (Hf x Zr 1-x O 2 ) nanocrystal memory using a very simple sol-gel spin coating method and 900°C 60 s rapid thermal annealing (RTA). From the transmission electron microscopy identification, the nanocrystals were formed as the monolayered charge trapping site after 900°C 60 s RTA and the size was ca. 5 nm. We verified the electrical properties in terms of program-erase speed, charge retention, and endurance. The sol-gel device exhibited the long charge retention time of 10 4 s with only 2.5% charge loss, and good endurance performance for program/erase cycles up to 10 5 .