Yi-Hong Wu

High-Program/Erase-Speed SONOS With In Situ Silicon Nanocrystals

In this letter, for the first time, we have successfully fabricated silicon-oxide-nitride-oxide-silicon (SONOS) devices with embedded silicon nanocrystals (Si-NCs) in silicon nitride using in situ method. This process is simple and compatible to modern IC processes. Different Si-NCs deposition times by in situ method were investigated at first. SONOS devices with embedded Si-NCs in silicon nitride exhibit excellent characteristics in terms of larger memory windows (> 5.5 V), lower operation voltage, high P/E speed, and longer retention time (> 108 s for 13% charge loss).

Novel Sub-10-nm Gate-All-Around Si Nanowire Channel Poly-Si TFTs With Raised Source/Drain

We have successfully fabricated novel sub-10-nm gate-all-around Si nanowire (NW) poly-Si TFTs with raised source/drain structure (GAA RSDNW-TFTs). The Si NW dimension is about 7×12 nm. A superior smooth elliptical shape is obtained, for the first time, in the category of poly-Si NW TFTs through the use of a novel fabrication process requiring no advanced lithographic tools. The GAA RSDNW-TFTs exhibit low supply gate voltage (3 V), steep subthreshold swing ~99 mV/dec, and high ION/IOFF >; 107 (VD = 1 V) without hydrogen-related plasma treatments. Furthermore, the DIBL of GAA RSDNW-TFTs is well controlled. These improvements can be attributed to the 3-D gate controllability, raised S/D structure, and sub-10-nm Si NW channel. These novel GAA RSDNW-TFTs are, thus, quite suitable for system-on-panel and 3-D IC applications.

Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals

In this paper, silicon-oxide-nitride-oxide-semiconductor (SONOS) devices with embedded silicon nanocrystals (Si-NCs) in silicon nitride using in situ method with multilevel and 2-b/cell operation have been successfully demonstrated. The proposed in situ Si-NC deposition method exhibits the advantages of low cost, simplicity, and compatibility with modern IC processes. SONOS memories with embedded Si-NCs exhibit a significantly improved performance with a large memory window (> 5.5 V), low operating voltage (P/E voltage: V_g = 6 V, V_d = 7 V and V_g = -7 V, V_d = 10 V, respectively), greater tolerable gate and drain disturbance (V_t shift <; 0.2 V), negligible second-bit effect, high P/E speed (after programming time = 10 μs with a 2-V shift of V_t under V_g = V_d = 6 V operation), good retention time (> 10⁸ s for 13% charge loss), and excellent endurance performance (after 10⁴ P/E cycles with a memory window of 3 V).

MILC-TFT With High-

In this letter, for the first time, one-time-programmable (OTP) memory fabricated on the low-temperature poly-Si p-channel thin-film transistor (TFT) with metal-induced lateral-crystallization channel layer and high-kappa dielectrics is demonstrated. The state of this OTP memory can be identified by the scheme of gate-induced drain leakage current measurement. The OTP-TFT memory has good electrical characteristics in terms of low threshold voltage Vth ~ -0.78 V, excellent subthreshold swing ~ 105 mV/dec, low operation voltage, faster programming speeds, and excellent reliability characteristics.

\kappa

In this letter, for the first time, a novel p-n-diode (PND) structure of SONOS-type thin-film transistor (TFT) nonvolatile memory (NVM) with embedded silicon nanocrystals (Si-NCs) in the silicon nitride layer using an in situ method is successfully demonstrated. This novel structure has many advantages, including high density and suitability for 3-D circuit integration. Hot-electron injection and hot-hole injection are used as the program and erase methods, respectively. The sensing current of the three-terminal PND-TFT NVM is 10-7 A by the band-to-band tunneling current. A much larger memory window (> 12 V) and good data retention time (> 108 s for 12% charge loss) are exhibited. The device appears to have great potential for system-on-panel applications.

Dielectrics for One-Time-Programmable Memory Application

This paper reports the impacts of NH3 plasma treatment time, oxide overetching depth, and gate oxide thickness on symmetric vertical-channel Ni-salicided poly-Si thin-film transistors (VSA-TFTs) for the first time. off-state currents may be improved by increasing the oxide overetching depth. The on/ off current ratio may be also improved by increasing the oxide overetching depth. The NH3 plasma optimum treatment time of VSA-TFTs is significantly shorter than that of conventional top-gate horizontal-channel TFTs. The performance of VSA-TFTs is degraded by NH3 plasma treatment for too long a time. VSA-TFTs with 15-nm gate oxide thickness display better subthreshold swing (<; 150 mV/dec) than VSA-TFTs with 30-nm gate oxide thickness. off-state currents can be improved by increasing Lmask, even when the oxide overetching depth and the gate oxide thickness are changed.

A Novel p-n-Diode Structure of SONOS-Type TFT NVM With Embedded Silicon Nanocrystals

We have successfully fabricated the symmetric vertical-channel Ni-salicided polycrystalline silicon thin-film transistors (VSA-TFTs) for the first time. The transfer characteristics of VSA-TFTs show a sharp turning between subthreshold and on state. The off -state currents can be improved by a modified overetching of oxide, equivalent dual-gate structure, and n⁺ floating-region length. The on-state currents can be enhanced by Ni-salicidation. The VSA-TFTs display a good subthreshold swing of 220 mV/dec, steep mobility increase (field-effect mobility of 76 cm²/V·s), and large on/off-current ratio of more than 10⁹ (<i>I</i>_OFF = 4 × 10^-14, <i>I</i>_ON = 7 × 10^-5, and <i>W</i>_mask/<i>L</i>_mask = 10 μm/3 μm).

Symmetric Vertical-Channel Nickel-Salicided Poly-Si Thin-Film Transistors With Self-Aligned Oxide Overetching Structures

A high programming speed with a low-power-consumption wrapped-select-gate poly-Si-oxide-nitride-oxide-silicon memory is successfully demonstrated using the novel dynamic threshold source-side-injection programming technique. The select gate embedded in such particular memory structure acts like a dynamic MOSFET resulting in programming current (I PGM) that can be enhanced in this DT mode, easily attaining a high programming speed of about 100 ns. It still doubles the memory density by achieving the 2-bit/cell operation with MLC under DT mode.

Novel Symmetric Vertical-Channel Ni-Salicided Poly-Si Thin-Film Transistors With High on/off-Current Ratio

In this paper, a reliability analysis of symmetric Vertical-channel Ni-SAlicided poly-Si thin-film transistors (VSA-TFTs) is performed for the first time. First, we compare the drain-induced barrier-lowering effect (DIBL) of VSA-TFTs. The VSA-TFTs with thinner gate oxide thickness, an offset structure, and a longer floating n+ region have better immunity to DIBL. Second, VSA-TFTs with a longer floating n+ region also have better immunity under hot-carrier (HC) stress and self-heating (SH) stress. However, VSA-TFTs with a shorter floating n+ region also have better immunity to positive gate bias (PGB) stress. Consequently, in order to optimize reliability characteristics, including SH stress, HC stress, and PGB stress, it is necessary to modulate the length of the floating n+ region. Third, the PGB stress, rather than SH stress or HC stress, becomes a major issue for VSA-TFTs under the stress bias below 4 V. In other words, PGB stress will dominate the degradation behaviors when the stress bias is not high enough to achieve SH stress and HC stress. Finally, the worst degradation condition of VSA-TFTs under HC stress, similar to that of most TFT devices, occurs when the stress of VG is less than half of VD.

High-Speed Multilevel Wrapped-Select-Gate SONOS Memory Using a Novel Dynamic Threshold Source-Side-Injection (DTSSI) Programming Method

For the first time, a programming mechanism for conventional source-side injection (SSI) (normal mode), substrate-bias enhanced SSI (body mode), and dynamic-threshold SSI (DTSSI) (DT mode) of a wrapped-select-gate SONOS memory is developed with 2-D Poisson equation and hot-electron simulation and programming characteristic measurement for NOR flash memory. Compared with traditional SSI, DTSSI mechanisms are determined in terms of lateral acceleration electric field and programming current (IPGM) in the neutral gap region, resulting in high programming efficiency. Furthermore, the lateral electric field intersects the vertical electric field, indicating that the main charge injection point is from the end edge of the gap region close to the word gate.