Yu-Hsien Lin

High-performance nonvolatile HfO/sub 2/ nanocrystal memory

In this letter, we demonstrate high-performance nonvolatile HfO/sub 2/ nanocrystal memory utilizing spinodal phase separation of Hf-silicate thin film by 900/spl deg/C rapid thermal annealing. With this technique, a remarkably high nanocrystal density of as high as 0.9 /spl sim/ 1.9 /spl times/ 10/sup 12/ cm/sup -2/ with an average size <10 nm can be easily achieved. Because HfO/sub 2/ nanocrystals are well embedded inside an SiO/sub 2/-rich matrix and due to their sufficiently deep energy level, we, for the first time, have demonstrated superior characteristics of the nanocrystal memories in terms of a considerably large memory window, high-speed program/erase (P/E) (1 /spl mu/s/0.1 ms), long retention time greater than 10/sup 8/ s for 10% charge loss, and excellent endurance after 10/sup 6/ P/E cycles.

Novel two-bit HfO/sub 2/ nanocrystal nonvolatile flash memory

This paper presents a novel nonvolatile poly-Si-oxide-nitride-oxide-silicon-type Flash memory that was fabricated using hafnium oxide (HfO/sub 2/) nanocrystals as the trapping storage layer. The formation of HfO/sub 2/ nanocrystals was confirmed using a number of physical analytical techniques, including energy-dispersive spectroscopy and X-ray photoelectron spectroscopy. These newly developed HfO/sub 2/ nanocrystal memory cells exhibit very little lateral or vertical stored charge migration after 10k program/erase (P/E) cycles. According to the temperature-activated Arrhenius model, we estimate that the activation energy lies within the range 2.1-3.3 eV. These HfO/sub 2/ nanocrystal memories exhibit excellent data retention, endurance, and good reliability, even for the cells subjected to 10 k P/E cycles. These features suggest that such cells are very useful for high-density two-bit nonvolatile Flash memory applications.

Low-Temperature Polycrystalline Silicon Thin-Film Flash Memory With Hafnium Silicate

In this paper, we have successfully fabricated poly-Si-oxide-nitride-oxide-silicon (SONOS)-type poly-Si-thin-film transistor (TFT) memories employing hafnium silicate as the trapping layer with low-thermal budget processing (les600degC). It was demonstrated that the fabricated memories exhibited good performance in terms of relatively large memory window, high program/erase speed (1 ms/10 ms), long retention time (>106 s for 20% charge loss), and 2-bit operation. Interestingly, we found that these memories depicted very unique disturbance behaviors, which are obviously distinct from those observed in the conventional SONOS-type Flash memories. We thought these specific characteristics are closely related to the presence of the inherent defects along the grain boundaries. Therefore, the elimination of the traps along the grain boundaries in the channel is an important factor for achieving high performance of the SONOS-type poly-Si-TFT Flash memory

High performance multi-bit nonvolatile HfO/sub 2/ nanocrystal memory using spinodal phase separation of hafnium silicate

In this paper, we exploit a novel technique for preparing high density HfO/sub 2/ nanocrystals with an average size > 10nm using spinodal phase separation of Hf-silicate thin film by 900/spl deg/C rapid thermal annealing for nonvolatile memories. The density can be as high as 0.9/spl sim/1.9/spl times/10/sup 12/cm/sup -2/. Owing to the fact that HfO/sub 2/ nanocrystals are well embedded inside SiO/sub 2/ matrix and their sufficiently deep energy level, we, for the first time, have demonstrated superior characteristics of the nanocrystal memory in terms of considerably large memory window, high speed program/erase (1 /spl mu/s/0.1ms), long retention time greater than 108s for 10/sup 8/s charge loss, excellent endurance after 10/sup 6/ P/E cycles, negligible read/write disturbances and multi-bit operation.

Annealing temperature effect on the performance of nonvolatile HfO2 Si-oxide-nitride-oxide-silicon-type flash memory

In this article, we demonstrate the effect of the postdeposition annealing for the HfO2 trapping layer on the performance of the Si-oxide-nitride-oxide-silicon-type flash memories. It was found that the memory window becomes larger while the retention and endurance characteristics get worse as the annealing temperature increases. This was ascribed to the larger amount and the shallower energy levels of the crystallization-induced traps as compared to the traps presented in the as-fabricated HfO2 film. Finally, in the aspect of disturbances, we show only insignificant read, drain, and gate disturbances presented in the three samples in the normal operation.

Impact of Channel Dangling Bonds on Reliability Characteristics of Flash Memory on Poly-Si Thin Films

In this letter, we fabricated the poly-Si-oxide-nitride-oxide-silicon (SONOS)-type Flash memories on polycrystalline-silicon thin films and found that dangling bonds presented along the grain boundaries in the channel significantly influence their reliability characteristics in the aspects of charge storage, drain disturbance, and gate disturbance. Employing a powerful defect passivation technique, i.e., NH3 plasma treatment, the charge storage capability was clearly observed to be remarkably improved. Even so, the hydrogenated polycrystalline-silicon thin-film transistors (poly-Si-TFTs) still suffered from serious drain and gate disturbances, which exhibited behaviors that are quite specific and undoubtedly distinct from those observed in the conventional SONOS-type memories on single crystalline substrates

2-bit poly-Si-TFT nonvolatile memory using hafnium oxide, hafnium silicate and zirconium silicate

In this paper, the authors, for the first time, have successfully fabricated SONOS-type poly-Si-TFT memories employing three kinds of high-k dielectrics, including HfO2, Hf-silicate and Zr-silicate, as the trapping layer with low-thermal budget processing. It was demonstrated that the fabricated memories exhibit good performance in terms of relatively large memory window, high program/erase speed (1ms/10ms), long retention time (>106s for 20% charge loss) and negligible read/write disturbances. In particular, 2-bit operation has been successfully demonstrated

Electric properties of SONOS memories with embedded silicon nanocrystals in nitride

Meng-Chien Hsieh, Tsung-Yu Chiang, Hua-An Dai, Chi-Ching Chen, Chen-Hao Chiang, Jia-Feng Wang, Yan-Jiun Lin, Ji-Ying He, Yan-Ning Chen, Tien-Sheng Chao, and Jenn-Fang Chen Department of Electrophysics, National Chiao Tung University, Hsinchu, Taiwan 30050, Republic of China Phone: +886-3-5712121 ext. 56152 E-mail: markvipmail@yahoo.com.tw Abstract This study investigates the electrical properties of SONOS memories with embedded silicon nanocrystals (Si-NC) in nitride. The interface states at the SiO2/Si-substrate interface are identified by experiment and simulation. Embedded Si-NCs in nitride are confirmed as a formation of Si-quantum dots in nitride. The Si-NCs form quantum confined states above their conduction band (CB). The electron capture time of the Si-quantum dots states is increased during programming carriers. This mechanism reveals that the Si-quantum dots states are effortless to program, and that the electrons on these states after programming can be reserved more easily. Introduction Metal–oxide–semiconductor (MOS) memories with embedded Si-NCs and silicon–oxide–nitride–oxide–silicon (SONOS) nonvolatile memories have recently attracted considerable attention because of their feasibility to overcome the limitations of conventional polycrystalline-silicon-based floating-gate memories [1]-[3]. Our previous works successfully demonstrated SONOS memories with embedded Si-NCs in silicon nitride [4]-[5]. This novel structure exhibits excellent characteristics in terms of larger memory windows, lower operation voltage, high P/E speed, and longer retention time. Nevertheless, the fundamental electric properties of this structure remain unknown. Experiments Figure 1 presents the device structure of the investigated samples. The SONOS memories with embedded Si-NCs are formed by ex situ deposition in nitride. Detailed growth conditions can be found elsewhere [4]-[5]. A series of various Si-NC size (no Si-NC (no_dot), small Si-NCs (small_dot), and large Si-NCs (dot)) are investigated in this work. The formation of Si-NCs was confirmed by atomic force microscopy [4]. Results and Discussion Figure 2 shows the capacitance-voltage (C-V) spectra (dashed line) of, and the corresponding simulation results (solid line) for, the investigated samples ((a) no_dot, (b) small_dot, and (c) dot). All of these samples have an additional capacitance peak in the positive bias region. The additional capacitance peak originates from the interface states at the SiO2/Si-substrate interface. The fundamental parameters (Dit (interface state density) and NQss (fixed oxide charges)) can be extracted by C-V simulation. The energy distributions of interface state density in the silicon band gap are extracted from C-V simulation, as shown in Fig. 3. These energy distributions are consistent with the previous non-annealing results [6]. The NQss are increased during the formation of Si-NCs. This result suggests that the embedded Si-NCs increase the number of trapping states in the oxide region, and trapping states are increased through enlarging the Si-NC size. Admittance spectroscopy was performed on these samples to investigate the emission time of the interface states. Figure 4 shows the temperature-dependent capacitance-frequency (C-F) spectra at bias of the additional capacitance maximum peak ((a) 2 V for no_dot, (b) 1.8 V for small_dot, and (c) 1.4 V for dot), and other biases of the additional capacitance peak exhibit the same temperature-dependent behavior. The dependence of the inflection frequency on temperature yields an activation energy (Ea) and a capture cross section (σ), as indicated in Table 1 (Ea, σ, and Ea from simulation). The similarity between the experimental activation energy and the simulated value at small bias confirms that the additional capacitance peak originates from the interface states at the SiO2/Si-substrate interface. The discrepancy at large bias is caused by the phonon-assisted tunneling in a large electric field [7], as shown in Fig. 5. Deep-level transient spectroscopy (DLTS) is applied in further investigation of the trapping states in the oxide region. Figure 6 shows the bias-dependent DLTS spectra of the investigated samples ((a) no_dot, (b) small_dot, and (c) dot). All of these samples have an apparent peak (Ei). The dot-sample has an additional peak (Ed) as the bias is swept from 2 to 3 V, as shown in Fig. 6 (c) (indicated by an arrow). According to the bias, emission time, and activation energy, the electric state of the apparent peak (Ei) originates from the interface state, which was analyzed above. Thus, the additional peak (Ed) of the dot-sample originates from the trapping states in the oxide region. Since these trapping states are not observed in the no_dot-sample, they are related to Si-NCs. These trapping states are examined in detail by simulating the band structure. Table 2 shows the activation energy (Ea) and capture cross section (σ) that were obtained from these trapping states by DLTS; the band structure simulation is based on the biases that were applied in this experiment. Figure 7 shows the simulated band structure for (a) VG= -2.24 V (flat-band voltage) and (b) VG= 1.8 V. This simulated band structure reveals that the Fermi level is close to Si-NCs when the trapping states are measured. This result demonstrates that the signal of the trapping states is produced by the Si-NCs. The simulation of the band structure reveals other important mechanisms. At applied biases of 2 V to 3.5 V, the Fermi level is swept through the CB of Si-NCs. This consequence reveals that the Si-NCs form quantum confined states above the CB of Si-NCs, and the trapping states below the CB of Si-NCs are probably the localized states that are produced by the composition fluctuation of Si-NCs. The above results demonstrate that embedded Si-NCs in nitride act as a formation of Si-quantum dots in nitride. Programming carriers is applied to understand the variation of electric properties after “WRITE” operation. Figure 8 shows the DLTS spectra of the dot-sample under three conditions ((a) no-programmed, (b) less-programmed, and (c) programmed). Excluding the voltage shift, the properties (activation energy and capture cross section) of the SiO2/Si-substrate interface states remain almost unchanged, as indicated in Table 3. Therefore, the time constant of the interface states at the SiO2/Si-substrate is fixed to observe the time constant of the Si-quantum dots states. The time constant of the Si-quantum dots states increases during programming carriers, as shown in Fig. 8 (indicated by an arrow), leading to the increase of the activation energy, as indicated in Table 4. Based on DLTS theory [8], the peak of the Si-quantum dots states originates from the hole emission or the electron capture. According to the simulation of the band structure, the peak of the Si-quantum dots states originates from the electron capture, and the time constant corresponds to the capture time of these states. The increase of the activation energy during programming carriers suggests that the electrons cannot easily be transported into Si-quantum dots states after programming carriers, and that the electrons on Si-quantum dots states also cannot easily be transported into the Si-substrate CB. Based on this mechanism, the Si-quantum dots states can be effortlessly programmed (~330 meV), and the electrons on these states after programming can be reserved more easily (~430 meV). Conclusions This study elucidates the fundamental electric properties of SONOS memories with embedded Si-NCs in nitride. Initially, the interface states at the SiO2/Si-substrate are identified by experiment and simulation. Embedded Si-NCs in nitride are confirmed as a formation of Si-quantum dots in nitride. The electron capture time of the Si-quantum dots states is increased during programming carriers. This mechanism suggests that the electrons on these states can be reserved more easily after programming. References [1] J. De Blauwe, IEEE Trans. Nanotechnol., vol. 1, no. 1, pp. 72–77, Mar. 2002. [2] P. Xuan, M. She, B. Harteneck, A. Liddle, J. Bokor, and T.-J. King, in IEDM Tech. Dig., 2003, pp. 609–613. [3] R. Ohba, N. Sugiyama, K. Uchida, J. Koga, and A. Toriumi, IEEE Trans. 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