Wentai Liu

Precise final state determination of mismatched CMOS latches

The effect on the metastability of mismatched FET parameters and load capacitances of CMOS latch/flip-flop is analyzed. Theoretical analysis based on small signal devices are provided. From this study we show that the final state depends on both initial voltages and latch mismatches. A novel method using state diagrams is proposed. On the state diagrams obtained by transient analysis of the latch, a straight line can be approximately drawn that defines two semi-planes. This straight line (the metastable line) determines precisely the final latch state, and gives a very good insight about the mismatches which exist in the latch. Several SPICE simulation results are shown for matched/mismatched flip-flops. They agree well with the theoretical ones. >

Metastability behavior of mismatched CMOS flip-flops using state diagram analysis

The effect on the metastability of the mismatch of FET parameters and load capacitances in a CMOS latch/flip-flop is analyzed. A novel method using state diagrams is proposed. On the state diagrams obtained by transient analysis of the latch, a straight line can be approximately drawn that defines two semiplanes, which precisely determine the latch final state. SPICE simulation results are shown for matched/mismatched flip-flops.

A two-layer channel routing algorithm for mixed analog and digital signal nets

The coupling of signals between sensitive nets by signals from digital and large-swing analog nets and effects of unwanted parasitic capacitances due to overlapping nets are a concern in the design of analogue VLSI circuits. A two-layer, detailed channel-routing algorithm for mixed analog and digital signal nets has been developed to address these problems. The algorithm accounts for capacitive coupling between nets on the same layer and on adjacent layers. It has been implemented in the C programming language.<<ETX>>

A monolithic 625 Mb/s data recovery circuit in 1.2 /spl mu/m CMOS

This paper presents a technique and circuitry for recovering high speed data using a novel matched delay sampler. By simultaneously propagating the data and a slow clock through two different delay taps, the sampler achieves a very fine sampling resolution which is mainly limited by the delay difference between data and clock. Thus it is capable of oversampling data signals and greatly enhances the possibility of very high rate data recovery. This circuitry has been designed in MOSIS 1.2 /spl mu/m CMOS technology with an area of 10.8 mm/sup 2/. Simulation shows it is capable of taking 625 Mb/s (SONET-OC12) input data and makes a 1:4 demultiplexing of the data into four 156.25 Mb/s output streams. In the processing of data recovery, the slow clock phase tracks with the input data based on values extracted from the digital phase control circuit.<<ETX>>

A CMOS signed multiplier using wave pipelining

The authors present a high-performance 8 /spl times/ 8 CMOS signed multiplier using the wave pipelining technique. The multiplier architecture is based on the modified Booth algorithm and Wallace-Tree techniques. At the transistor level, a biased CMOS gate is used to balance the path delays; it provides a means of postprocess tuning, even though it has a disadvantage in power consumption. The multiplier is implemented with MOSIS 2-/spl mu/m technology, and simulation results show a tenfold speed-up over nonpipelined operation.

CMOS sampler with 1 Gbit/s bandwidth and 25 ps resolution

A technique and circuitry for real-time high-resolution sampling of a digital waveform are presented. This circuitry has been fabricated in 1.2 /spl mu/m CMOS technology, and test results show a bandwidth of up to 1 Gbit/s for the digital data and a sampling resolution externally adjustable between 25 ps and 250 ps. The fabricated circuit has shown sampling stability, monotonicity, and uniformity in sampling resolution.

Scalable VLSI implementations for neural networks

This paper discusses research on scalable VLSI implementations of feed-forward and recurrent neural networks. These two families of networks are useful in a wide variety of important applications—classification tasks for feed-forward nets and optimization problems for recurrent nets—but their differences affect the way they should be built. We find that analog computation with digitally programmable weights works best for feed-forward networks, while stochastic processing takes advantage of the integrative nature of recurrent networks. We have shown early prototypes of these networks which compute at rates of 1–2 billion connections per second. These general-purpose neural building blocks can be coupled with an overall data transmission framework that is electronically reconfigured in a local manner to produce arbitrarily large, fault-tolerant networks.

Skew and delay minimization of high speed CMOS circuits using stochastic optimization

For certain high speed CMOS circuits, e.g. clock drivers, wave-pipelined circuits, it is very important to limit the spread in circuit delay as well as the worst-case delay. The delay spread or skew, is caused by the data-dependency of the circuit delay. To reduce the effect of process and environmental variations on skew and circuit delay, the transistors in a CMOS circuit need to be carefully sized. In this paper, we present a stochastic optimization approach to transistor sizing. Each sizing scheme considered during optimization is evaluated through accurate circuit simulations to determine the delay and skew values. The power of the optimization technique enables us to generate very good siting schemes with few simulations, as demonstrated by the example given here.<<ETX>>

Mixed-mode simulation tools for custom VLSI designs

A system for performing concurrent VLSI simulation on a distributed processing system is presented. The system provides an expandable medium which allows the coexistence of existing different-level simulation programs. Several design examples including various word-length Manchester carry-chain adders, Booth-encoded multipliers, and one stage of a two-dimensional fast Fourier transform circuit have been simulated using RNL at the switch level, FACTS at the electrical level, and Lisp routines at the functional level. The largest circuit simulated thus far contains 29000 transistors and was simulated in 24 concurrent processes executing on four SUN III workstations. The system can be further enriched by integrating other existing behavior, register-transfer, and logic level simulation programs. The possibility of integrating an analog-circuit simulation program is currently being investigated.<<ETX>>

Design and implementation of a two-dimensional fast Fourier transform chip

The authors describe a rasterized pipelined architecture for performing a two-dimensional fast Fourier transformation (2DFFT). Incorporating over 152,000 transistors in 1.25 mu m CMOS on a 9 mu m die, the chip functions at a clock speed of 10 MHz, processing a 256*256-pixel image at a real-time frame rate of 30 Hz. The input and output data formats are rasterized streams of 22-bit fixed-point complex numbers. The authors present the chip architecture and describe the design of its constituent units. On-chip storage of the sine/cosine factors and the absence of a corner-turning memory are this designs most novel features.<<ETX>>A description is given of a rasterized, pipelined architecture for performing a two-dimensional fast Fourier transformation (2DFFT). A chip has been designed for implementing this architecture in 1.25- mu m CMOS. Each chip consist of 152 transistors on a 9-mm die. The chips operate at a clock speed of 10 MHz and process a 256*256-pixel image at a real-time rate of 30 Hz. Each chip has input and output data formats consisting of rasterized streams of 22-bit fixed-point complex numbers. The authors present the chip architecture and describe the design of its constituent units. On-chip storage of the sine/cosine factors and the absence of corner-tuning memory are the most novel features.<<ETX>>