Werner Geurts

Processor modeling and code selection for retargetable compilation

Embedded processors in electronic systems typically are tuned to a few applications. Development of processor-specific compilers is prohibitively expensive and, as a result, such compilers, if existing, yield code of an unacceptable quality. To improve this code quality, we developed a processor model that captures the connectivity, the parallelism, and all architectural peculiarities of an embedded processor. We also implemented a retargetable and optimizing compiler working on this model. We present the graph-based processor model, and formally define the code generation task as binding the intermediate representation of an application to this model. We also present a new method for code selection, based on this processor model, that is capable of handling directed acyclic graphs instead of trees.

A graph based processor model for retargetable code generation

Embedded processors in electronic systems typically are tuned to a few applications. Development of processor specific compilers is prohibitively expensive and as a result such compilers, if existing, yield code of an unacceptable quality. To improve this code quality, we developed a retargetable and optimising code generator. It uses a graph based processor model that captures the connectivity the parallelism and all architectural peculiarities of an embedded processor In this paper; the processor model is presented and we formally define the code generation task, including code selection, register allocation and scheduling, in terms of this model.

Testability analysis in high level data path synthesis

This article discusses the cooperation of testability and High Level Data Path Synthesis (HLDPS). A particular target domain, namely real time digital signal processing, is addressed where the generation of customized data path compositions is one of the crucial steps during the HLDPS. Taking the testability cost into account during the HLDPS strongly depends on the test generation tool in use. It requires a test tool for which the capabilities have to be amenable to modeling on a high level. For this purpose, a novel sympolic test pattern approach is presented which is based on symbolic controllability and observability descriptions. These symbolic descriptions are calculated on the building block level and are also very useful for analyzing the testability problems in an early stage of the HLDPS. Our experiments show that the calculation and evaluation of these descriptions is very efficient and fast enough for the HLDPS to explore many data path alternatives.

Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suite

SoCs will soon have to integrate tens of complex system functions, each with their own optimal balance of performance, flexibility, energy consumption, communication, and design time. The traditional model of a (configurable) general-purpose processor core with a number of hardware accelerators no longer suffices. Application-specific instruction-set processors (ASIPs) can offer the right balance for each system function, and thus form the basis of new generations of multi-core SoCs. This presentation introduces Chess/Checkers, a retargetable tool suite available from Target Compiler Technologies, enabling the design of ASIPs in multi-core SoCs. Chess/Checkers offers fast architectural exploration, hardware synthesis, software compilation, inter-ASIP communication, and verification. The tools support a broad range of architectures, from small microprocessors, over DSP dominated cores, to VLIW and vector processors

ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces

We developed a point-to-point, low latency, 3D torus Network Controller integrated in an FPGA-based PCIe board which implements a Remote Direct Memory Access (RDMA) communication protocol. RDMA requires ability to directly access the remote node application memory with minimal OS or CPU intervention. To this purpose, a key element is the design of a direct memory writing mechanism to address the destination buffers; on Virtual Memory supporting OSes this corresponds to a number of page-segmented DMAs. To minimally affect overall performance, mechanisms with lowest possible latency are needed for either Virtual-to-Physical address translation and registered buffers list scanning. In a first implementation these tasks were set on a soft-core µ C on the FPGA, leading to a 1.6? µ s latency to process a single packet and limiting the peak bandwidth. As a second trial, we present an accelerated version for these time-critical network functions exploiting an application-specific processor (ASIP) designed using a retargetable ASIP development toolsuite that allows architectural exploration. Benchmark results for Buffer Search and Virtual-to-Physical tasks on the ASIP show improvements for latency with up to ten times lower cycles cost compared with the soft-core µ C . RDMA needs independent memory management by the NIC in host/GPU virtual address space.This requires fast lookup of buffers and Virtual-to-Physical address translation.We developed an ASIP for the FPGA to accelerate these operations with good results.ASIP design has been effective thanks to architecture exploration toolsuite.

Optimal scheduling and software pipelining of repetitive signal flow graphs with delay line optimization

Software pipelining can have an enormous impact on the clock cycle count and hence on the performance of a real-time signal processing design. Because it pays off to invest CPU time in the optimal software pipelining of time-critical parts of a design, an integer programming approach is proposed for simultaneous scheduling and software pipelining. The integer programming techniques in the literature do not support cyclic (repetitive) signal flow, graphs, and/or do not allow optimization of the storage cost of delay lines during software pipelining. The new contributions in this paper are the full integration of software pipelining and scheduling, based on a new timing model that supports cyclic signal flow, graphs and optimization of delay line storage costs. Experiments with several real-time signal processing applications have shown the practical applicability of the approach.<<ETX>>

Solving large scale assignment problems in high-level synthesis by approximative quadratic programming

• Algorithms for physical design automation • Memory management algorithms for digital signal processin g, multimedia applications, embedded systems • High-level synthesis, system-level exploration • Configurable and reconfigurable systems • Compiler/microarchitecture interaction • Data-flow analysis and code restructuring • Mathematical programming, combinatorial optimization te chniques and applications in VLSI CAD