Dirk Lanneer

Chess : Retargetable Code Generation for Embedded DSP Processors

This chapter introduces Chess, a retargetable code generation environment for fixedpoint DSP processors. Chess addresses a range of commercial as well as applicationspecific processors, which are increasingly being used for embedded applications in telecommunications, speech and audio processing. Chess is based on a mixed behavioural/structural processor representation model, which can account for many architectural peculiarities that are typical for fixed-point DSP processors. In addition, the code generator is employing a number of efficient optimisation techniques. These features result in highly optimal machine code.

Architectural synthesis for medium and high throughput signal processing with the new Cathedral environment

Integrating highly complex signal-processing systems in an application-specific way is becoming an economic necessity for system industry today. In recent -’ears, research in high-level or architectural synthesis has therefore attempted to bridge the existing gap between systems and (custom) architectures. This effort has been complementary to the work on physical integration, which bridges the gap from detailed architecture to final implementation in, for instance, a custom ASIC, a sea-of-gates or a PLD realisation. The ability to handle real-life design problems is however still one of the most important challenges for researchers in these fields.

PROGRAMMABLE CHIPS IN CONSUMER ELECTRONICS AND TELECOMMUNICATIONS

Mobile and personal communication systems, and multi-media are among the most prominently growing sectors of the electronics industry today. As an illustration, Figure 1 gives an indication of the volume of some personal communication applications in the European market. New business and home applications are emerging, using advanced communication media such as satellite links, cellular radio, or high-speed optical networks. The success of these developments will however depend to a great extent on the ability to realise complex digital signal processing functionalities in cost-efficient VLSI chips.

Efficient microcoded processor design for fixed rate DFT and FFT

Many Fourier transform applications have to operate at fixed sample rates in the low to medium range, especially in signal processing systems. Hence, in order to arrive at efficient implementations, hardware-sharing is required as in microcoded architectures. In this paper, very efficient application-specific realizations spanning a wide throughput range are proposed for both DFT and FFT algorithms. Novel single-cycle address computations are presented for the FFT to obtain these results. Trade-offs between the architectural alternatives are provided too. These designs have been used as test-vehicles for the architectural strategy in an automated synthesis tool-box tuned towards signal processing applications.

An integrated automatic design system for complex DSP algorithms

An integrated design environment for the automated design of DSP systems is described. The overall design time of complex DSP systems on silicon can be reduced drastically by offering the designer a complete silicon compilation environment, integrating architectural level synthesis tools, a module generator and a floorplanner. The system is supported by a flexible and powerful library. A true exploration of the design space in an interactive way is possible. Examples of the first complex chips that have been designed with this system are discussed.