Gert Goossens

Instruction set definition and instruction selection for ASIPs

Application Specific Instruction set Processors (ASIPs) are field or mask programmable processors of which the architecture and instruction set are optimised to a specific application domain. ASIPs offer a high degree of flexibility and are therefore increasingly being used in competitive markets like telecommunications. However, adequate CAD techniques for the design and programming of ASIPs are missing hitherto. An interactive approach for the definition of optimised microinstruction sets of ASIPs is presented. A second issue is a method for instruction selection when generating code for a predefined ASIP. A combined instruction set and data-path model is generated, onto which the application is mapped.<<ETX>>

Optimized synthesis of asynchronous control circuits from graph-theoretic specifications

Synthesis support for the design of asynchronous circuits is crucial. The synthesis method proposed starts from a graph-theoretic specification called a signal transition graph (STG). This work deals with the theoretical foundations of a method to transform a given STG into an STG that satisfies the original timing behavior and that in addition obeys the unique state coding requirement. It is shown that in general, many valid solutions to this problem are possible. The authors find a transformed STG that can be realized in a circuit with optimized speed and area. >

High-Level Synthesis for Real-Time Digital Signal Processing

1. Introduction. 2. DSP Architecture Synthesis. 3. Implementation of Data Structrues. 4. Implementation of High-Level Operations. 5. Implementation of Control Functions. 6. Scheduling. 7. Structure Generation. 8. Demonstrator Designs. References. Index.

Embedded software in real-time signal processing systems: application and architecture trends

We present an extensive survey of trends in embedded processor use with an emphasis on emerging applications in wireless communication, multimedia, and general telecommunications. We demonstrate the importance of application-specific instruction-set processors (ASIPs) in high-volume, low cost applications. We also examine some of the underlying trends of the applications in which embedded processors are used. This is followed by a description of embedded software development tool requirements. High-performance software compilation emerges as a key requirement. Finally, specific industrial case studies of products in MPEG, videophone, and low-cost digital signal processor (DSP) applications are used to illustrate the architecture design tradeoffs, and highlight specific tool requirements. A companion paper (Goosens et al., 1997) presents a comprehensive survey of embedded software development tools, focusing mostly on retargetable software compilation.

Combined hardware selection and pipelining in high-performance data-path design

At the highest abstraction level, the specification of a data path consists of a number of interconnected abstract building blocks and a constraint on the minimal clock frequency. An algorithm which optimally selects hardware blocks for implementing these abstract building blocks is presented. A technique for hierarchical redistribution and insertion of pipeline registers is also presented. Finally, the two optimization tasks are combined. This combination makes the area tradeoff between the cost of additional speedup circuitry and pipeline registers possible. The techniques are based on accurate hierarchical timing models for the hardware blocks. The automation relieves the designer of the numerous, time-consuming critical path verifications and area evaluations that are required to explore the large design space. The implementation of the algorithms has resulted in a CAD tool called HANDEL, embedded in the data-path compiler CHOPIN. >

Specification and analysis of timing constraints in signal transition graphs

The introduction of timing constraints in signal transition graphs (STG) is discussed. The possible interpretations of these timing constraints (called the firing semantics) is also discussed. During synthesis it is an important task to calculate the minimum and maximum distance in time between two transitions based on timing information present in the STG. A new recursive algorithm that calculates this time difference is presented. It takes into account some of the firing semantics introduced before. The algorithm finds the correct result for acyclic graphs in a quadratic worst case running time.<<ETX>>

Processor modeling and code selection for retargetable compilation

Embedded processors in electronic systems typically are tuned to a few applications. Development of processor-specific compilers is prohibitively expensive and, as a result, such compilers, if existing, yield code of an unacceptable quality. To improve this code quality, we developed a processor model that captures the connectivity, the parallelism, and all architectural peculiarities of an embedded processor. We also implemented a retargetable and optimizing compiler working on this model. We present the graph-based processor model, and formally define the code generation task as binding the intermediate representation of an application to this model. We also present a new method for code selection, based on this processor model, that is capable of handling directed acyclic graphs instead of trees.

A graph based processor model for retargetable code generation

Embedded processors in electronic systems typically are tuned to a few applications. Development of processor specific compilers is prohibitively expensive and as a result such compilers, if existing, yield code of an unacceptable quality. To improve this code quality, we developed a retargetable and optimising code generator. It uses a graph based processor model that captures the connectivity the parallelism and all architectural peculiarities of an embedded processor In this paper; the processor model is presented and we formally define the code generation task, including code selection, register allocation and scheduling, in terms of this model.

Embedded software in real-time signal processing systems: design technologies

The increasing use of embedded software, often implemented on a core processor in a single-chip system, is a clear trend in the telecommunications, multimedia, and consumer electronics industries. A companion paper (Paulin et al., 1997) presents a survey of application and architecture trends for embedded systems in these growth markets. However, the lack of suitable design technology remains a significant obstacle in the development of such systems. One of the key requirements is more efficient software compilation technology. Especially in the case of fixed-point digital signal processor (DSP) cores, it is often cited that commercially available compilers are unable to take full advantage of the architectural features of the processor. Moreover, due to the shorter lifetimes and the architectural specialization of many processor cores, processor designers are often compelled to neglect the issue of compiler support. This situation has resulted in an increased research activity in the area of design tool support for embedded processors. This paper discusses design technology issues for embedded systems using processor cores, with a focus on software compilation tools. Architectural characteristics of contemporary processor cores are reviewed and tool requirements are formulated. This is followed by a comprehensive survey of both existing and new software compilation techniques that are considered important in the context of embedded processors.

An Efficient Microcode-Compiler for Custom DSP-Processors

In this paper, a microcode compiler for custom DSP-processors is presented. This tool is part of the CATHEDRAL II silicon compiler. Two optimization problems in the microcode compilation process are highlighted: microprogram scheduling and memory allocation. Algorithms to solve them, partly based on heuristics, are presented. Our compiler successfully handles repetitive programs, and is able to decide on hardware binding. In most practical examples, optimal solutions are found. Whenever possible, indications of the complexity are given.