Michael Goroll

Degradation of moulding compounds during highly accelerated stress tests. A simple approach to study adhesion by performing button shear tests

High temperature storage can degrade moulding compounds for chip encapsulation to such an extent that the adhesion to surfaces like copper (lead frames) or polyimide (chip coating) decreases drastically causing delamination. Also during normal operation of electronic components heat is generated locally (bond wire or chip surface) degrading the moulding compound and reducing the adhesion which in extreme cases can destroy the metallisation or the bond wires.

New aspects in characterization of adhesion of moulding compounds on different surfaces by using a simple button-shear-test method for lifetime prediction of power devices

The knowledge of moulding compound adhesion on different surfaces inside a semiconductor package is fundamental to ensure high reliability of the devices. The most susceptible interfaces are the boundary surfaces between moulding compound/chip and moulding compound/lead frame. The adhesion properties of these interfaces are influenced by various material and process parameters for chip surface and bond pad conditioning. The knowledge of the zero hour adhesion state and the possible degradations during reliability stress tests like e.g. high temperature storage (HTS) or temperature cycling (TC) is the base to perform a trusty lifetime prediction. This paper shows the principle of button-shear-test method offering the determination of adhesion in a quantitative way. The influence of different moulding compound materials, polyimide layers and bond pad conditioning on moulding compound adhesion on silicon is described by corresponding force-displacement diagrams. Degradation effects of moulding compound adhesion on copper lead frames after performing HTS stress tests is presented and will be discussed. For high accelerated HTS tests the possibility of test time reduction by a factor of 10 compared to automotive qualification standards AEC-Q100/101 is discussed in the paper based on performed experiments (Automotive Electronic Council, 2003, 2005 [1,2]).

Exceptional operative gate voltage induces negative bias temperature instability (NBTI) on n-type trench DMOS transistors

Abstract In some automotive applications, high negative bias is used to faster switch off n-type devices. This exceptional operative gate voltage at relative high temperature can induce instability of device parameters (e.g. threshold voltage, transconductance, saturation current, etc. In this work we will show that positive charge trapping generated under exceptional negative bias can induce large threshold voltage shift. Even if the effect can partially recover during the standard operative condition, nevertheless large Vth, shift are still present and can affect the correct functionality of the device.

Acoustic detection of micro-cracks in small electronic devices

Abstract We demonstrate the feasibility of in-situ acoustic detection of micro-cracks in small electronic devices. Applying precisely controlled damage to test vehicles using a nanoindenter, we record brittle fracture of thin layers by means of an ultra-sound piezo sensor, which is able to detect micro-cracks in the moment they emerge. This robustness test does not require further preparation effort that may induce additional stress to a sample or modify it physically, inhibiting unambiguous failure analysis. With regard to its applicability and limitations, we put acoustic emission into context with standard ex-situ experimental procedures for crack characterization in micro-electronic structures.

Determination of adhesion and delamination prediction for semiconductor packages by using Grey Scale Correlation and Cohesive Zone Modelling

Abstract Adhesion of moulding compounds on different surfaces like silicon, copper or silver is the most important parameter to optimise with regards delamination behaviour of a semiconductor package. Standard material characterisation methods like Thermo-Mechanical Analysis (TMA) or Dynamic Mechanical Analysis (DMA) do not fully cover this essential parameter. This paper presents results from moulding compound adhesion measurements obtained by using the Button-Shear-Test (BST). The interface cracking of a specimen was analysed by Deformation-Measurement-by-means-of-Correlation (DAC) technique which is based on Grey Scale Correlation. Using knowledge of the crack opening derived from DAC, a methodology to determine fracture energies which are necessary to remove the button from the dedicated surface is shown. Based on these energies the possibility of delamination prediction of semiconductor packages by using the Cohesive Zone Modelling (CZM) is described. This simulation approach is demonstrated for a TO220 package and compared with temperature cycle test results. The aspect of material pre-selection by evaluating adhesion in reliability stress tests like High Temperature Storage (HTS) is also discussed.

Analysis of ESD protection structure behaviour after ageing as new approach for system level reliability of automotive power devices

Abstract ESD (electrostatic discharge) protection devices as part of the device pad circuitry of semiconductors are designed for a specific wafer technology and ESD withstanding voltage. After successful qualification they will be released for a usage in high volume products where they must ensure the ESD robustness over the complete product lifetime. All present automotive qualification standards e.g. AEC (automotive electronic council) or JEDEC do not cover the assessment of the typical drifts of the characteristic electrical ESD protection device parameters after application of device specific reliability stress tests under consideration of the target ESD stress [Automotive Electronic Council, AEC-Q100-Rev-F, 2003; Automotive Electronic Council, AEC-Q101-Rev-C, 2005; JEDEC JP-001, Foundry Process Qualification Guideline, 2002]. The paper introduces a methodology to characterize ESD protection diodes after ageing by BTS (bias temperature stress) reliability tests. The used devices are partly ESD pre-stressed before application of the reliability test. The influence of the reliability stress on the ESD robustness is evaluated by using an ESD post-stress. The experimental results are presented and discussed. For ESD protection devices release targets for automotive power applications are defined.

New aspects for lifetime prediction of bipolar transistors in automotive power wafer technologies by using a power law fitting procedure

Abstract Bipolar transistors are part of the design manuals of almost all semiconductor wafer technologies. These design library devices must be qualified and released according to the present qualification standards, e.g. AEC (automotive electronic council) or JEDEC [Automotive Electronic Council. AEC-Q100-Rev-F; 2003; Automotive Electronic Council. AEC-Q101-Rev-C; 2005; JEDEC JP-001. Foundry process qualification guideline; 2002]. Dedicated stress tests (e.g. high temperature electrical operation (HTEO), bias temperature stress (BTS) or emitter base reverse bias (EBRB)) must be performed to check device specific drift and degradation mechanisms. A lifetime prediction must be performed on base of the determined device parameter drifts. The mentioned qualifications tests are arranged at typical device application conditions for electrical operation and temperature. Due to the breakdown behaviour of bipolar transistors the electrical operation parameters are limited to the save-operation-area (SOA). This excludes the possibility of any acceleration during these tests. Based on this fact the final check of the requested device lifetime in customer applications can be performed only by non-accelerated end-of-life tests. The paper shows a review of typical stress tests of dedicated bipolar transistors of an automotive power wafer technology. A presentation of the drift behaviour of the current gain (beta) parameter as function of stress time and qualification test is presented. In order to replace the end-of-life test requirement and to find a new approach to estimate the expected lifetime in the final device application a power law fitting procedure will be introduced. New aspects to discuss these results with respect to the defined lifetime target will be shown.

Degradation of moulding compounds during highly accelerated stress tests – A simple approach to study adhesion by performing button shear tests

High temperature storage can degrade moulding compounds for chip encapsulation to such an extent that the adhesion to surfaces like copper (lead frames) or polyimide (chip coating) decreases drastically causing delamination. Also during normal operation of electronic components heat is generated locally (bond wire or chip surface) degrading the moulding compound and reducing the adhesion which in extreme cases can destroy the metallisation or the bond wires.

Reduction of test effort. Looking for more acceleration for reliable components for automotive applications

Abstract Experience shows that chip package interaction is a dominant cause for failures of electronic components. Optimising the technology by applying the standard temperature cycling test to detect these failures is very time consuming and not any more compatible with today’s development cycles. Early failure indicators (preferable electrically measurable) could be the key element to reduce the test effort and to guarantee the performance in an application. From the package point of view there are three main drivers to be taken into consideration: The temperature, i.e. all degradation processes with an activation energy, temperature swings, which cause thermo-mechanical stress due to different CTE (coefficient of thermal expansion) of the variety of different materials used for the assembly, and temperature gradients, especially when active cycles are applied (switching of the device) can lead to metal reconstruction and plastic deformation, reducing lifetime of the component drastically. Knowledge of the weak areas allows choosing the best test in order to make the addressed failure mode observable in the shortest time. This paper provides a decision basis to speed up technology qualification by using TS (thermal shock) instead of TC (thermal cycling). Results will be shown for different die attach materials.

ESD protection structure qualification – a new approach for release for automotive applications

Abstract To protect semiconductor products against damages due to electrostatic discharges separate protection structures are necessary. These structures are part of the device pad circuitry and designed for a dedicated wafer technology and ESD ( Electrostatic Discharge ) withstanding voltage. All present automotive qualification standards AEC-Q100/101 ( Automotive Electronic Council ) [1,2] do not cover a qualification and release of ESD protection structures related to their designed ESD strength. The paper will introduce a new qualification strategy for ESD protection structures depending on the designed ESD target. On dedicated ESD diodes drifts of several parameters versus time were analyzed. The results will be presented and discussed. Release targets for automotive applications will be defined.