Josef Winnerl

Pipelined architecture for fast CMOS buffer RAMs

A novel pipeline architecture for CMOS static RAMs (SRAMs) that allows operation at very high clock rates is described. Basic requirements for achieving high speed are the implementation of a hierarchical architecture and a memory cell with separate READ and WRITE data lines. The access speed of hierarchically organized memory blocks was between 2.5 and 3.5 ns. The maximum operating frequency of a 16 K pipelined hierarchical SRAM (PHSRAM) is in the range of 300 MHz. The hierarchical architecture and a seven-transistor memory cell provide a circuit using digital swings all over. Key advantages of the full-swing static logic circuitry are robustness with respect to fabrication tolerances and a high-noise immunity. Moreover, the circuit can be reduced to finer structure sizes without any redesign, since there are no critical analog circuit parts. >

Static and transient latch-up hardness in N-well CMOS with on-chip substrate bias generator

Theoretical considerations and experimental results of the influence of an on-chip substrate bias generator on static and transient latch-up hardness in n-well CMOS are presented. The current drive capability of the VBBgenerator is limited, its internal resistance is operating point dependent. If the VBBgenerator is not capable to sink the static and the time averaged transient substrate currents, localized forward biasing of the substrate takes place, thus triggering latch-up. A special clamp circuit was used for limiting the forward substrate bias below the value capable to trigger the parasitic SCR. Using such clamping techniques the latch-up hardness with on-chip bias generator can significantly be improved during power-up and in normal operation mode.

Improvement of latchup hardness by geometry and technology tuning

A latchup characterization method for CMOS technologies is presented. By separating the role of the parasitic bipolar transistors and the well and substrate shunt efficiencies, the interplay of geometry and technology becomes evident. An optimization of the device latchup hardness is achieved by partitioning the n/sup +/-p/sup +/ spacing with respect to the well. Substrate trigger currents depend on technological features such as substrate doping, well doping, and epilayer thickness. >

Ring Oscillator Structure For realistic Dynamic Stress Of MOSFETS And Interconnects

In this paper a ring oscillator structure is proposed that allows to investigate degradation of MOS transistors and interconnection lines under dynamic stress conditions. The elements of the ring oscillator are dynamically stressed close to real operation conditions. Nevertheless only a simple DC supply voltage is required, Hot carrier degradation of the MOS transistors can be accelerated by operating the oscillator at an elevated supply voltage and at reduced temperature. Increasing the temperature selectively adkelerates the electromigration degradation of interconnection lines.

Pipelined 16k Buffer RAM with 300MHz Operating Frequency

A new pipeline architecture for fast CMOS buffer SRAMs is presented that allows operation at very high clock rates. The high speed is achieved by use of a hierarchical architecture and a memory cell with separate read and write data lines.

Influence of transistor degradation on CMOS performance and impact on life time criterion

For more realistic lifetime predictions of CMOS technology a stress test was developed that yields the relevant transistor degradation under dynamic stress and simultaneously the impact of transistor degradation on circuit speed performance. Thus uncertainties with respect to duty factor estimations and special dynamic effects are eliminated. The influence on circuit performance can be directly characterized by the change of ring oscillator frequency. The relative frequency change was found to be about one order of magnitude similar than the transconductance change. Based on these results, a less restrictive criterion is introduced. If 1-2% frequency change is allowed the acceptable Delta g/sub m//g/sub m/ (where g/sub m/ is the extrinsic transconductance) can be increased from the typical value of 10% to 25%, resulting in an considerably increased lifetime. For a given lifetime this can be utilized to reduce the gate length from 1 mu m to 0.4 mu m without reducing the supply voltage, extending the use of 5-V supply voltage into the deep sub- mu m regime.<<ETX>>

Reduced n + /p + -spacing with high latchup hardness in self-aligned double well CMOS technology

Latchup in CMOS circuit with an epitaxial layer originates from short channel effects of the parasitic field oxide transistors and from voltage drops on shunt resistances. The short channel behaviour of the field oxide transistors was improved by reducing the p-well depth and modifying the local oxidation step for the well generation. By laser scanning microscope it is shown that for the conventional well latchup firing occurs at the bulges of the well boundary. Using the shallow well the charge compensated region at the well boundary and thereby the latchup sensitive bulges are eliminated. With shallow p-well the shunt resistances are reduced by diminished out-diffusion of the heavily doped n+-substrate and by feasible use of a thinner epi-layer. These measures enable to reduce the critical n+/p+-spacing of adjacent n-and p-channel transistors from 12 µm to 6µm without loosing latchup hardness.

Silicides for Highly Integrated Memory and Logic Circuits

State of the art DRAM and logic processes widely make use of silicides formed by refractory metals like Ta, Mo, W, Ti, Co, or others. The methods for silicide formation range from sputtering, reaction with predeposited metal, to selective CVD deposition. The most common application of silicides in state of the art CMOS processes is to use them as a conducting layer that can withstand high temperature processes and that has a significantly lower sheet resistivity than doped mono or poly crystalline silicon. Besides their role as a temperature stable conductor silicides have further interesting properties when using them as a diffusion source for impurities to generate shallow junctions, or as an alternative gate material with a work function in the middle of the silicon band gap. Based on the example of the self aligned silicidation with titanium silicide the limitations of the state of the art technology will be shown and requirements for future applications will be discussed.

Critical charge model for transient latch-up in VLSI CMOS circuits

Experimental results and theoretical considerations on the critical charge model for latch-up in VLSI CMOS circuits are presented. The critical charge is constant, proportional to the trigger phase pulse height, and inversely proportional to the trigger pulse width. With these results it is possible to calculate the transient latch-up susceptibility of circuits due to periodic pulses, e.g. overshoot, undershoot, and glitches.<<ETX>>

Latch-up Free CMOS Using Buried Polysilicon Diodes

Latch-up free CMOS circuit operation is achieved through the use of buried polysilicon diodes instead of conventional (ohmic) well contacts. In a DRAM technolgy with polysilicon bit line a buried polysilicon diode can be realized with no additional process step and no additional die area is required. No degradition of MOS device parameters occurs. The basis for experiment is a 4M DRAM 0.9μm n-well CMOS technology with substrate bias generator [1].