Wilfried Hansch

Carrier transport near the Si/SiO2 interface of a MOSFET

Abstract We present a rigorous investigation of carrier transport near the semiconductor-insulator interface of a MOSFET. Deriving a new current equation we include the quantum mechanical correction on the carrier density distribution near the interface. This equation also contain a new mobility model for the surface field reduced channel mobility, that is derived from Boltzmanns equation. We implemented this new equation into the device simulator MINIMOS and discuss its consequences to real devices.

THE EVOLUTION OF THE MINIMOS MOBILITY MODEL

Abstract The paper reviews the evolution of the mobility model of the MINIMOS program for the two-dimensional simulation of miniaturized MOS devices over a period of 10 years.

MINIMOS 3: A MOSFET simulator that includes energy balance

We present a model for hot carrier transport which is implemented in the device simulator MINIMOS 3. A brief resume of the model is given. We present various results which were calculated with this new model. We show that the I-V characteristics of a MOSFET can be calculated from Leff= 10 µm down to Leff= 0.9 µm with one parameter set. Modifications of carrier and current distributions are presented that show how hot carrier effects tend to smooth these distributions. Implications are discussed how a self-consistent carrier temperature can be used to model impact ionization and oxide injection.

A novel approach for including band‐structure effects in a Monte Carlo simulation of electron transport in silicon

We present a novel approach for including the effects of realistic silicon band structure in the simulation of electron transport with a Monte Carlo method. This will be achieved by an electron effective‐mass and energy–over–wave‐vector relation, which are derived directly from the density of states. Consistent with this model, the scattering rates as well as the equations of motion are determined by the density of states. With our approach the computation tables in three‐dimensional momentum space can be replaced by one‐dimensional tables in energy space. The necessary amount of memory size and table lookup time is therefore significantly reduced. The number of free parameters in our model is not higher than in the full band‐structure model. We show by comparison with full band‐structure Monte Carlo and experimental results that there is no loss in physical meaning by the use of the new method.

Hot carrier hardness analysis of submicrometer LDD devices

A detailed analysis of the degradation of various lightly doped drain (LDD) devices is presented. Technology parameters that are varied are gate length, LDD n-dose, and energy for devices with 20-nm gate oxide. Different DC stress conditions are investigated. To gain insight into the degradation process a simulation tool is used that self-consistently calculates the oxide damage during a DC stress experiment. This enables the location and amount of oxide charges and interface states due to hot carrier injection to be obtained. The relationship between stress-induced damage and device hot carrier hardness is discussed. >

The electron high‐energy distribution function: A comparison of analytical models with Monte Carlo calculations

We compare the high‐energy distribution function of the lucky electron model, the Maxwellian distribution, and the asymptotic solution of Boltzmann’s equation with Monte Carlo calculations in the effective‐mass approximation. We show that the Monte Carlo calculations are in good agreement with the asymptotic solution of Boltzmann’s equation for constant and for space‐dependent electric fields while the other distributions do not agree with the Monte Carlo results.

Hot carrier relief of metal oxide semiconductor field effect transistor by using work-function engineering

A detailed analysis of hot-carrier-degraded NMOS and PROS devices with either n+ or p+ gates is presented. For this analysis, we utilized a new simulation tool which allows direct monitoring of the buildup of charge and interface states during the DC stress experiments. The impact of the work-function difference of the n+ and p+ gate material on the injection conditions of hot carriers into the gate oxide will also be considered. Our results indicate that both NMOS and PMOS FETs with p+ gates are superior regarding hot-carrier stability.

Long-term bias temperature reliability of P/sup +/ polysilicon gated FET devices

An instability was found to be associated with +BT stress for P/sup +/ poly-gated NMOSFETs (PNMOS) and PMOSFETs (PPMOS), but not with the N/sup +/ poly-gated devices (NNMOS and NPMOS). The instability with the P/sup +/ poly-gated devices, which is a decrease in threshold voltage (V/sub t/) and an increase in interface state density (D/sub it/), was significantly reduced following N/sub 2/ annealing at 400/spl deg/C. It is shown that adequate reliability for P/sup +/ poly-gated devices can be achieved for VLSI technologies. >

High Capacitance Isolated Surrounding Stacked Trench Cell For Advanced DRAMs

High density trench type memory cells have been fabricated with silicon islands formed by a grid of trenches. The thin poly-silicon capacitor electrodes surround almost the total cell area and are isolated from the substrate. Due to the large capacitor area very high cell capacitances can be achieved which makes this cell concept shrinkable up to the 256M-DRAM generation.

A 64MBit Stacked-Trench-Capacitor Cell

Implementation of very thin capacitor electrodes and of a new multilayer dielectric has been rcalized in a Stacked-Trench-Capacitor Cell with 64I\dbit-DRAM feature sizes. Cell capacitances in the range of 35fF are obtained at a trench depth of 5pm. The cell exhibits a relatively flat topolog)r and good device characteristics like low leakage currents and c-particle sensitivity due to the electrical isolation of the capacitor from the substrate. Key features of the technolog5r, device parnmeters, and memory array performance will be discussed.