Udo Schwalke

EXTIGATE: The ultimate process architecture for submicron CMOS technologies

In this work, we present the novel process architecture EXTIGATE (EXtended Trench Isolation GAte TEchnology) which solves major problems associated with shallow-trench-isolation (STI) and n/sup +//p/sup +/ dual workfunction gate technology. These achievements are realized without increasing process complexity or cost. Furthermore, the process window for planarization is enlarged leading to a robust, submicron n/sup +//p/sup +/ gate STI-CMOS process ideally suited for low-voltage CMOS applications.

Strain relaxation and its effect on radiation‐induced interface traps in thin rapid thermally grown high‐temperature oxides

The radiation response of metal‐oxide‐semiconductor capacitors containing thin (50–150 A) high‐temperature (1200 °C) oxides grown by rapid thermal oxidation (RTO) and conventionally furnace‐grown (800 °C) oxides are investigated by means of capacitance‐voltage techniques. The results indicate that the Si/SiO2 interface is largely controlled by the oxide growth process. The prominent interface‐trap state at Emg+0.2 eV, which characterizes furnace grown oxides is strongly suppressed in high‐temperature RTO oxides. The improved radiation hardness is attributed to strain relaxation by viscous oxide flow which occurs during oxidation at 1200 °C.

Direct observation of very slow traps after homogeneous charge injection in MOS capacitors

Abstract A modification of the quasistatic CV-method is presented which allows the charging time of very slow traps to be measured and slow and fast interface states in a metal-oxide-semiconductor (MOS) system to be distinguished. Applying this method to MOS capacitors after Fowler Nordheim charge injection gives strong evidence that in addition to fast interface states very slow traps are created near the semiconductor interface. These are charged by tunnelling rather than a thermally activated processes.

Through-the-gate-implanted ultrathin gate oxide MOSFET's with corner parasitics-free shallow-trench-isolation

We have realized direct-tunneling (DT) gate oxide (1.6 nm) NMOS and PMOS transistors by means of through-the-gate-implantation in a corner parasitics-free shallow-trench-isolation CMOS technology. In order to take full advantage of in situ cluster-tool processing and to preserve initial wafer-surface quality, the essential part of the MOS gate is fabricated prior to device isolation and through-the-gate-implantation is utilized for well- and channel-doping. In addition, a fully-reinforced-gate-oxide-perimeter is provided and trench corner parasitics are eliminated by the advanced process architecture without increasing process complexity. Fully functional direct-tunneling oxide MOSFETs with excellent electrical characteristics confirm the feasibility of this novel approach.

Measurement of the threshold voltage in MOS capacitors by the equilibrium controlled static C-V method

Abstract The equilibrium-controlled static C-V procedure continuously monitors the displacement current during the C-V sweep. The relaxation time needed to re-establish equilibrium after small gate bias increments as a function of gate voltage, provides a first direct measure of the threshold voltage in MOS capacitors. In addition, the inversion charge can be determined as a function of gate bias from the monitored displacement current transients, which leads to a definition of threshold voltage in close relation to that used in MOS transistors. The validity of these approaches is demonstrated by investigating MOS capacitors on n-type and p-type substrates with different doses of threshold implants. The results are compared with threshold voltages measured by conventional procedures on respective MOS transistors.

Suppression of the Reverse Short Channel Effect in (Sub-)0.25um nMOSFETs using elevated S/D structures

nMOSFETs with elevated S/D structures were fabricated by selective epitaxial growth of in-situ doped S/D regions. Variation of the total thermal budget allowed the optimization of outdiffusion from the epi-Si with respect to the realization of shallow junctions. For all process conditions investigated the Reverse Short Channel Effect (RSCE) was completely suppressed indicating that the RSCE observed for conventional processed nMOSFETs has to be attributed to S/D implantation. The process presented allows a realization of typical advantages for elevated S/D structures with an optimized Vth roll-off.

Realization and Evaluation of an Ultra Low-Voltage/Low-Power 0.25um (n+/p+) Dual-Workfunction CMOS Technology

1 2 & The decrease in supply voltage is the most effective approach to reduce power consumption in CMOS circuits. Accordingly, the ultimate goal for many low-power applications is aimed at a single-battery operation with a nominal supply voltage of 1.2V and an end-of-life voltage of 0.9V. On the other hand, circuit performance is often sacrified when supply voltage (Vdd) is reduced. In order to compensate for the loss in drive current, threshold voltage (Vth) is reduced. This approach, however, requires an n+/p+ gate technology /1/ with optimized gate workfunction for Nand PMOS devices to achieve sufficient performance at low voltage and still maintain good short channel behavior as well as low off-leakage (Ioff).