Paul Janis Timans

Radiative Properties of Patterned Wafers With Nanoscale Linewidth

Temperature nonuniformity is a critical problem in rapid thermal processing (RTP) of wafers because it leads to uneven diffusion of implanted dopants and introduces thermal stress. One cause of the problem is nonuniform absorption of thermal radiation, especially in patterned wafers, where the optical properties vary across the wafer surface. Recent developments in RTP have led to the use of millisecond-duration heating cycle, which is too Short for thermal diffusion to even out the temperature distribution. The feature size is already below 100 nm and is smaller than the wavelength (200-1000 nm) of the flash-lamp radiation. Little is known to the spectral distribution of the absorbed energy for different patterning structures. This paper presents a parametric study of the radiative properties of patterned wafers with the smallest feature dimension down to 30 nm, considering the effects of temperature, wavelength, polarization, and angle of incidence. The rigorous coupled wave analysis is employed to obtain numerical solutions of the Maxwell equations and to assess the applicability of the method of homogeniwtlon based on effective medium formulations.

Millisecond Annealing: Past, Present and Future

The challenge of achieving maximal dopant activation with minimal diffusion has re-awakened interest in millisecond-duration annealing processes, almost two decades after the initial research in this field. Millisecond annealing with pulsed flash-lamps or scanned energy beams can create very shallow and abrupt junctions with high concentrations of electrically active carriers, but solutions for volume manufacturing must also meet formidable process control requirements and economic metrics. The repeatability and uniformity of the temperature cycle is the key for viable manufacturing technology, and the lessons from the development of commercial rapid thermal processing (RTP) tools are especially relevant. Advances in the process capability require a fuller understanding of the trade-off between dopant activation, defect annealing. diffusion and deactivation phenomena. There is a strong need for a significant expansion of materials science research into the fundamental physical processes that occur at the short time scales and high temperatures provided by millisecond annealing.

Challenges for ultra-shallow junction formation technologies beyond the 90 nm node

The continuing scaling of MOS devices poses increasing challenges for the formation of ultra-shallow junctions (USJ). At the 90 nm device node USJ requirements for PMOS devices include junction depth below 25 nm and sheet resistance below 660 /spl Omega//square. Success in volume manufacturing also requires excellent repeatability and wafer uniformity, including optimization with respect to wafer pattern effects. This paper shows that sophisticated spike-annealing techniques combined with low-energy ion implantation can meet these requirements. For the 65 nm node, current methods will have to be augmented with optimized preamorphization and co-implantation techniques. The paper also examines the potential of new techniques such as millisecond annealing and solid-phase epitaxy (SPE). For millisecond annealing one of the major challenges arises from greatly magnified pattern effects combined with the very large thermal stresses induced by the enormous temperature gradients imposed on the wafer. SPE can provide the very shallow, highly activated junctions needed for advanced technologies but the issues of process integration and residual damage will require further development.

RTP application and technology options for the sub-45 nm nodes

As device dimensions have reduced to nanometer length scales, rapid thermal processing (RTP) has emerged as the key approach for providing the low thermal budget and ultra-pure process conditions that are essential in advanced fabrication schemes. As further progress in electronic technology becomes increasingly dependent on success in rapid development cycles that include both materials innovations and changes in CMOS device architecture, RTP will play a major role in the story. RTP will contribute in gate-stack engineering, oxidation processes, ultra-shallow junctions, silicide formation, low-k dielectric annealing and in fundamental improvement of thin film properties. As device dimensions are controlled at the atomic scale, the concepts of thermal budget reduction will continue to drive the technology, with reductions in both process times and process temperatures combined with control of a very high purity process gas ambient. The thermal and ambient flexibility of RTP will become even more important as processes are developed and optimized for new gate dielectrics, high-mobility channel designs and metal gates combined with device architecture changes such as multiple-gate transistor designs. As the transistor channel length scales towards the ultimate limit imposed by atomic-scale fluctuations and quantum effects, the need for minimization of parasitic resistance and capacitance will become increasingly dominant in device performance. Here, the most critical requirements are to increase the concentrations of electrically active dopants without inducing excessive diffusion and to reduce contact resistances. These challenges will be met through innovation in RTP that addresses opportunities in materials engineering and in thermal cycle design. Further advances in silicon device technology will ultimately be limited by manufacturing costs. Pressure for manufacturing cycle-time reductions will mean that single-wafer processing technologies, including RTP, will continue to displace batch processing approaches. The final blow for the batch furnace will come from the transition to even larger wafer sizes, where the planar heating geometry inherent in RTP provides a natural fit to the wafer

The future of RTP, a technology that can change the IC fab industry

RTP presents a unique opportunity for the semiconductor industry. By completing the transition to RTP as we enter the 300 mm-era, the industry can seize the opportunity for significant improvements in cycle-time, in thermal budget minimization and in process performance. This paper examines how RTP has evolved to meet these challenges and describes the state-of-the-art of RTP technology today. The poor throughput performance of 300 mm batch furnaces, the risk of misprocessing large batches of very valuable wafers and the inflexibility of the furnace in an era when cycle-time is paramount all signal the end of large-batch thermal processing within this decade.

Uniformity optimization techniques for rapid thermal processing systems

This paper presents two efficient robust methods for uniformity optimization of rapid thermal processes. Both of these methods involve the reuse of empirical response surfaces linking zone powers to measured process data created on a baseline system. The first method uses fossilized gain matrices from the baseline system, while the second method involves customization of the baseline response surface for each system. The approaches use the response surfaces for iterative modification of zone powers to reduce the process nonuniformity on successively processed wafers. These methods are applied to the optimization of rapid thermal oxidation processes on several lamp-heated rapid thermal processing systems. Most of the uniformity improvement is obtained with the first two optimization runs; in some instances, the process is optimized to less than 1% 1-sigma nonuniformity with the use of just two wafers. Because the response surfaces from the baseline system can be reused for all similar systems, considerable savings in time and wafers are realized.

A Short History of Pattern Effects in Thermal Processing

Radiant energy sources enable rapid and controllable thermal processing of wafers with closed-loop control of wafer temperature. However the use of energy sources that are not in thermal equilibrium with the wafers makes the heating process sensitive to the optical properties of the wafers. In particular, patterns on wafer surfaces can cause temperature non-uniformity at length scales where lateral thermal conduction cannot smooth out the effect. Such “pattern effects” are even more significant for advanced processing techniques like millisecond annealing and pulsed laser annealing, because of the extremely large heating powers employed. The issue of pattern effects was recognized early on in the development of radiant heating technology, but has recently become a critical issue for process control. Despite the challenges, many counter-measures can be deployed to minimize pattern effects, including modifications to the wafer design, changes in processing recipe and equipment configuration. Such solutions have enabled the use of radiant heating for even the most demanding device fabrication applications.

Pattern effects and how to explore them

Pattern effects in RTP are of increasing interest as device feature sizes decrease because of their strong impact on process uniformity and defect generation, but it has been recognized that they can sometimes be difficult to diagnose. In the literature pattern effects in production are discussed and how they affect overlay shifts. Pattern effects within test structures and their evaluation are described as well. This paper emphasizes the comparison of pattern effects with semiempirical calculations as an evidence for the existence of such pattern induced temperature inhomogeneities. Starting with the heat conduction equation a temperature profile from a pattern structure was derived and this is compared with the measured sheet resistance (R/sub S/) distribution after RTP on a chessboard-patterned wafer that had been ion implanted on the opposite side to the pattern. The R/sub S/ distribution suggests good agreement between theoretical and measured temperature distributions. Examples of how to overcome such pattern effects are shown. Also different approaches are presented of how to measure and visualize pattern-induced non-uniformities.

Millisecond Annealing for Semiconductor Device Applications

Over the last decade millisecond annealing (MSA) has made the transition from a research tool to a key manufacturing technology for advanced complementary metal-oxide-semiconductor (CMOS) devices. MSA provides several unique process capabilities that have been very helpful for continued scaling of CMOS. One early application was for improving carrier activation in polysilicon gate electrodes, which reduces carrier depletion effects, providing increased gate capacitance. MSA also enables the formation of highly activated ultra-shallow junctions (USJ), which is essential for controlling short-channel effects while simultaneously minimizing the transistor’s parasitic resistance. New applications have emerged in silicide annealing, especially for NiSi contacts, where MSA can reduce the tendency for dopant deactivation, film agglomeration and for formation of “pipe defects”. As device scaling continues, the need to limit atomic diffusion and defect formation calls for ever-decreasing thermal budget, opening up new opportunities for MSA. Furthermore, the processing has to be compatible with new materials, including high-K dielectrics and metal gates, as well as the features needed for strain engineering and new channel materials. Millisecond annealing is usually performed through the use of pulsed high-power flash-lamps or scanned continuous wave laser beams. The paper describes the relative merits of these approaches, including flash-assisted RTP™ (fRTP™), where rapid wafer preheating is combined with pulsed surface heating to provide great flexibility in the design of thermal profiles. Such flexibility helps optimization in the trade-off between between dopant activation, diffusion, defect annealing and device integration requirements. Another important topic is process control, including issues of wafer temperature measurement and process uniformity. Finally the paper discusses emerging applications for millisecond annealing as a manufacturing technology for new types of semiconductor devices.

Optimization of diffusion, activation and damage annealing in millisecond annealing

Advances in CMOS technology require continuous reductions in the thermal budget employed for activating ion implanted dopants. However, low thermal budget annealing approaches, such as millisecond annealing, must also remove implant damage to minimize junction leakage. This paper explores the trade-offs between dopant diffusion, electrical activation and damage annealing for ultra-shallow junctions (USJ) formed by low energy B implants into both crystalline and pre-amorphized silicon. The study also addressed how low-thermal budget annealing affects the use of strong halo-style doping from As implants. Several annealing methods were studied, with the main focus on flash-assisted RTP™ (fRTP™) at temperatures between 1250°C and 1350°C. Activation was assessed with RsL™ non-contact measurements and Hg-probe four point-probe sheet resistance measurements, as well as a continuous anodic oxidation technique for depth profiling of carrier concentrations and mobility. Residual damage was assessed by photoluminescence, thermal wave studies, optical reflectance and RsL junction leakage current measurements. fRTP effectively activates high-dose, low-energy B implants, while limiting the diffusion to a few nm of profile movement. The limited thermal budget of millisecond annealing reduces, but does not fully eliminate, implant damage from heavy ions implanted at high energy, although very high process temperatures, e.g. ∼1300°C, are more effective in this regard. Strong halo doping greatly increases the junction leakage and for future device nodes it will be important to reduce implantation damage from both USJ and halo implants. Non-invasive damage metrology can help rapid optimization of implantation and annealing conditions. Such measurements will be even more useful when quantitative models can accurately link them to doping and damage profiles.