William Bereza

Design considerations for 2nd-order and 3rd-order bang-bang CDR loops

This paper examines two popular bang-bang CDR architectures: one is with a conventional RC loop filter which often involves a 3rd order loop design and the other is with a separate proportional path which involves a straightforward 2nd order loop design. Design considerations for the two architectures are compared as a function of various design parameters that impact jitter tolerance. Theoretical findings are confirmed by experimental results of a wide-range bang-bang CDR fabricated in 90nm CMOS

A signal integrity-based link performance simulation platform

This paper embodies a methodology used to create high-speed transceiver behavior models employed within a signal integrity-based link simulation platform. This tool includes routines for the optimization of transmitter pre-emphasis and equalization. This platform was created using MATLAB, qualified against Agilents ADS SI suite, and correlated with measurements. This paper also describes the practical uses of such a simulator developed at Altera to predict link performance over backplanes.

PELE: Pre-emphasis a Equalization Link Estimator to Address the Effects of Signal Integrity Limitations

This paper discusses a methodology employed to create a tool that quantifies the effects of signal integrity limitations particularly for high-speed applications. The tool is based on a platform of routines which predict performance over high-speed links. It contains routines that optimize transmitter pre-emphasis and receiver equalization that lead to superior BER performance. The tool is qualified against Agilents ADS simulator and correlated to measurements

Nonlinear behavior study in digital bang-bang PLL

A simple high-performance nonlinear digital PLL is fabricated in 90 nm CMOS with operating range of 0.5 to 3.25 GHz and 1.24 ps jitter. New insights into the PLL behavior are discussed. The classical “20Log” in-band phase noise tracking does not hold for the type of nonlinear digital loops.

Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs

A 275mW at 6.375Gbps high speed serial interface developed in TSMCs 90nm triple-gate oxide CMOS process and the customized methodology applied to develop and integrate high-speed mixed-signal IPs into FPGA platforms is presented. The risk reduction approach used ensured reliable product, with timely availability. The transceiver IP supports multiple protocols such as PCIe, XAUI, CEI, SDI, etc. There are as many as 20 Rx/Tx transceiver channels embedded in the FPGA. The transceiver achieves better than 10-12 BER at 6.375Gbps across the XAUI backplane originally designed for 3.125Gbps

Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-A

The modeling and simulation of an all-digital PLL is presented. Verilog-A, owing to its flexibility, is used to create both behavioral and gate-level models used in system-level and circuit-based simulation. The methodology presented allows us to simulate the PLL closed-loop and accurately take into account reference phase noise, DCO phase noise, quantization noise and any excess of it, allowing us to validate our jitter budget for any given application.