Tim Tri Hoang

Architecture and methodology of a SoPC with 3.25Gbps CDR based SERDES and 1Gbps dynamic phase alignment

The SoPC (system on a programmable chip) aspects of the Stratix GX/spl trade/ FPGA with 3.125 Gbps SERDES are described. The FPGA was fabricated on a 0.13 /spl mu/m, 9-layer metal process. The 16 high-speed serial transceiver channels with clock data recovery (CDR) provides 622-Megabits per second (Mbps) to 3.125-Gbps full-duplex transceiver operation per channel. Another challenge described is the implementation of 39 source-synchronous channels at 100 Mbps to 1 Gbps, utilizing dynamic phase alignment (DPA). The implementation and integration of the FPGA logic array (with its own hard IP) with the CDR and DPA channels involved grappling with SoC design issues and methodologies.

A jitter equalization technique for minimizing supply noise induced jitter in high speed serial links

As data rate of serial interface has increased dramatically, timing margin has gotten tighter and tighter. Supply voltage has also kept deducing according to silicon process technology. However, supply noise is hardly reduced due to higher data rate, a huge number of transistors and slower improvement of packaging technology. Therefore, the jitter due to supply noise can be quite large compared to other jitter components. The jitter due to supply noise is not cancelled out by CDR or PLL at the receiver since PDN resonance frequency is higher than loop bandwidth of CDR or PLL. It is not cost effective if only PDN improvement is adopted to reduce supply noise induced jitter. It is essential to optimize performance at architecture level including circuits and PDN. In this paper, the new technique is proposed to minimize supply noise induced jitter in high speed serial interface. The proposed techniques called Jitter Equalizer (JEqualizer) improves jitter performance by 80% with minimal power increase and area over head. The impact is evaluated by supply noise induced jitter modeling.

Arria™ 10 device architecture

This paper presents the architecture of Arria 10, a high-density FPGA family built on the TSMC 20SOC process. The design of the device includes an embedded dual-core 1.5 GHz ARM A9 subsystem with peripherals, more than 1M logic elements (LEs) and 1.7M user flip-flops, and 64Mb of embedded memory organized into configurable memory blocks. The Arria 10 family is also the first mainstream FPGA family to include hardened single-precision IEEE 754 floating point, with an aggregate throughput of 1.3 TFLOPs. Device I/O consists of 28G programmable transceivers with an enhanced PMA architecture hardened PCIe sub-blocks and hardened DDR external memory controllers. New methods for digitally-assisted analog calibration are used to address process variation. The fabric is optimized for an aggressive die-size reduction and power improvement over 28nm FPGAs and includes features such as time-borrowing FFs for micro-retiming, tri-stated long-lines for improved routability, programmable back-bias at LAB-cluster granularity and power-management features such as Smart-VID for balancing leakage and performance across the process distribution.

Receiver Offset Cancellation in 90-nm PLD Integrated SERDES

A wide-range transceiver was designed and fabricated in a 90-nm TSMC CMOS logic process. Each transceiver channel contains a transmitter and receiver with clock data recovery (CDR) circuit. The range of operation for this transceiver is from 622 Mbps to 6.5 Gbps. Voltage offsets in the receive path degrade the performance of the transceiver by putting a lower bound on the precision with which a data bit can be measured In addition to raising the minimum input voltage that can be correctly detected by the CDR, offsets in receive path cause duty cycle distortion, which, added with inter symbol interference (ISI), reduce the overall margin of data recovery directly worsening the bit error rate (BER). Presented in this paper is a methodology to cancel voltage offsets in the receive path with a soft intellectual property (IP) core programmed in the PLD.