William F. Stonecypher

A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques

A 5 Gb/s source-synchronous signaling system was developed utilizing a new clock/data skew minimization technique. The method incorporates a transmit clock delay line and integrating receiver yielding an increased tolerance to high frequency transmit source jitter. The system has the potential to support rapid turn-on without the clock buffer latency of conventional source-synchronous systems. A second method to minimize clock distribution delays with embedded clocking via superposition of clock in the common-mode across two differential pairs was also explored. A test device was fabricated in TSMCs 40 nm LP CMOS process and performance measurements indicate substantial margin improvements, even when the matched source-synchronous system is subjected to realistic source SJ and independent PSIJ noise. Comparable performance was also achieved with embedded common-mode clocking with matched peak swings, indicating it as a potential solution for pin-constrained designs.

Transition-limiting codes for 4-PAM signaling in high speed serial links

As signaling rates move to multi-gigahertz frequencies and multi-level schemes are used to increase bit rates, intersymbol interference becomes a key issue for signal integrity. The paper discusses the use of coding techniques to minimize ISI on channels using embedded clocking and 4-PAM signaling. The coding techniques are designed to increase timing and noise margins, while guaranteeing minimum transition density for clock recovery. The elimination of the worst case pattern sequences reduces peak and mean-square distortion. The results from the coded versus uncoded sequences are compared across several channel environments. The probability of symbol error and the related performance bounds are calculated. Simulations were used to verify the analytical models. The proposed codec blocks were synthesized, so that their implementations could be compared in terms of resulting latency, gate-count and area.

Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system

High speed serial data transceivers often employ sophisticated communication techniques to balance out the effects of material loss and reflections. Link control hardware is required to initialize and adapt the link in a variety of signaling environments, often using loops with time constants which are orders of magnitude larger than the data unit interval (UI). This presents a big problem for the link modeling and verification, especially when link is a part of a larger digital system. We describe here the modeling and simulation method that overcomes this problem. The method is based on a standard hardware description language (HDL) and is applied to a fully adaptive, multi-mode, high-speed serial link system in a 36-channel switch fabric ASIC, designed in 0.13/spl mu/m CMOS process.