William H. Howland

Product wafer measurements of MOS gate dielectric quality with a small diameter elastic probe

A new metrology method has been developed for the monitoring of advanced gate dielectric processes associated with 0.1 μm technology. Unlike previous techniques that involved corona or Hg gate based methods, this technique measures all gate dielectric parameters on product as well as monitor wafers. This is accomplished with a specially designed small area elastic pressure probe contacting the gate oxide within the scribe lines of 200 or 300 mm wafers. The elastic probe method utilizes a semiconductor compatible material, which is specially conditioned to produce a nondamaging, highly repeatable contact. Extensive damage evaluations have been performed and indicate that no observable physical or electrical damage is introduced into the silicon by these pressure contacts. Critical parameters such as equivalent oxide thickness (EOT), threshold voltage, channel doping profile, oxide and interface trap charge, and leakage current can be determined with high precision and accuracy. For example, EOT repeatabili...

In‐line, Non‐destructive Electrical Metrology of Nitrided Silicon Dioxide and High‐k Gate Dielectric Layers

Highly sensitive, accurate and precise methods for measuring the properties of dielectrics used in sub 0.13 μm technology are required. It is particularly critical to monitor the electrical properties of the gate dielectric. The electrical properties of thin dielectrics are assessed with a new, non‐contaminating, non‐damaging elastic probe. This probe forms a small diameter (∼30 μm to 50 μm ) Elastic Metal gate (EM‐gate) on the surface of a dielectric. Subsequent electrical measurements are made with advanced Capacitance‐Voltage (CV), Conductance‐Voltage (GV), and Current‐Voltage (IV) techniques. Valuable and essential information about the dielectric thickness and quality, leakage current, Si‐SiO2 interface quality, and channel carrier density profile is obtained.

Product wafer monitoring of ultrashallow channel implants with an elastic metal gate

The most critical parameter for deep submicron metal–oxide–semiconductor (MOS) field effect transistors (MOSFETs) is the threshold voltage (VT). The device VT is highly dependent on processing; specifically, the ion implanted channel-doping profile. Monitoring the channel doping on product wafers is highly desirable and is a major issue for process engineers. A technique based on a noncontaminating, nondamaging, small diameter metal contact is described for highly sensitive and precise measurements of the channel carrier density profile, dose and VT on product wafers.

Electrical characterization of silicon-on-insulator structures with a nondamaging elastic–metal gate

This article explores electrical characterization methods for silicon-on-insulator (SOI) structures with a nondamaging elastic metal gate (EM gate). Important material electrical properties related to the top silicon layer, gate dielectric and interfaces, and buried oxide are addressed. The techniques utilized are currently under development for SOI and are based on EM-gate capacitance–voltage methods, current–voltage methods, and a back channel metal–oxide–semiconductor transistor that utilizes elastic probes to form a temporary source and drain.

Electrical characterization of ultra-thin oxides and high K gate dielectrics

The performance of deep submicron devices depends heavily on the electrical properties of the gate dielectric. Electrical properties such as dielectric constant, leakage current density, interface trap and oxide trapped charge, dielectric integrity, and reliability are all critical concerns for the development of advanced gate dielectrics. This paper discusses several metrology methods based on capacitance-voltage (CV), charge-voltage (QV) and current-voltage (IV) and reviews the problems, issues and concerns associated with CV and IV metrology as IC technology has gone from 1 μm down to 0.18 μm and beyond. Issues such as proper measurement setup, equivalent circuit effects, silicon accumulation capacitance, and quantum confinement of the silicon density of states must be accounted for. In addition to these considerations, the influence of interfacial layers between the gate and the dielectric needs to be addressed. These interfacial layers can consist of organics, inorganics, and water. The paper include...