Robert J. Hillard

Accurate Sheet Resistance Measurement on Ultra-Shallow Profiles

Comparison of state-of-the-art zero-penetration sheet resistance tools on ultra-shallow Boron CVD layers on top of a medium doped As layer.

Measurements of Ultra-Shallow Junction (USJ) Sheet Resistance with a Non-Penetrating Four Point Probe

An accurate method to measure the four point probe (4PP) sheet resistance (Rs) of USJ Source-Drain structures is described. The new method utilizes Elastic Material probes (EM-probe) to form non-penetrating contacts to the silicon surface. The probe design is kinematic and the force is controlled to ensure elastic deformation of the probe material. The probe material is selected so that large direct tunneling currents can flow through the native oxide thereby forming a low impedance contact. Sheet resistance measurements on USJ implanted P+/N structures with SIMS junction depths as shallow as 15 nm have been measured. The sheet resistance values obtained with the new EMprobe 4PP method were found to be consistent with expectations. In this paper, the method will be demonstrated on a variety of implanted USJ structures.

Product wafer measurements of MOS gate dielectric quality with a small diameter elastic probe

A new metrology method has been developed for the monitoring of advanced gate dielectric processes associated with 0.1 μm technology. Unlike previous techniques that involved corona or Hg gate based methods, this technique measures all gate dielectric parameters on product as well as monitor wafers. This is accomplished with a specially designed small area elastic pressure probe contacting the gate oxide within the scribe lines of 200 or 300 mm wafers. The elastic probe method utilizes a semiconductor compatible material, which is specially conditioned to produce a nondamaging, highly repeatable contact. Extensive damage evaluations have been performed and indicate that no observable physical or electrical damage is introduced into the silicon by these pressure contacts. Critical parameters such as equivalent oxide thickness (EOT), threshold voltage, channel doping profile, oxide and interface trap charge, and leakage current can be determined with high precision and accuracy. For example, EOT repeatabili...

In‐line, Non‐destructive Electrical Metrology of Nitrided Silicon Dioxide and High‐k Gate Dielectric Layers

Highly sensitive, accurate and precise methods for measuring the properties of dielectrics used in sub 0.13 μm technology are required. It is particularly critical to monitor the electrical properties of the gate dielectric. The electrical properties of thin dielectrics are assessed with a new, non‐contaminating, non‐damaging elastic probe. This probe forms a small diameter (∼30 μm to 50 μm ) Elastic Metal gate (EM‐gate) on the surface of a dielectric. Subsequent electrical measurements are made with advanced Capacitance‐Voltage (CV), Conductance‐Voltage (GV), and Current‐Voltage (IV) techniques. Valuable and essential information about the dielectric thickness and quality, leakage current, Si‐SiO2 interface quality, and channel carrier density profile is obtained.

Product wafer monitoring of ultrashallow channel implants with an elastic metal gate

The most critical parameter for deep submicron metal–oxide–semiconductor (MOS) field effect transistors (MOSFETs) is the threshold voltage (VT). The device VT is highly dependent on processing; specifically, the ion implanted channel-doping profile. Monitoring the channel doping on product wafers is highly desirable and is a major issue for process engineers. A technique based on a noncontaminating, nondamaging, small diameter metal contact is described for highly sensitive and precise measurements of the channel carrier density profile, dose and VT on product wafers.

Monitoring the micro-uniformity performance of a spinning disk implanter

Abstract Methods for monitoring fluctuations in dose uniformity on spatial scales on the order of 1 cm or less are investigated for the case of a spinning disk ion implanter. Various optical, electrical and physical methods including Therma-Wave signals, optical reflectance, sheet resistance, spreading resistance and Rutherford backscattering are used. Comparison is made to a number of estimates of dose uniformity as a function of beam size and the scanned distance between successive passes through the ion beam.

Advanced Gate and Stack Dielectric Characterization with FastGate® Technology

In this paper a non‐damaging and non‐contaminating method for performing Capacitance‐Voltage (CV) and Current‐Voltage (IV) electrical characterization of advanced gate dielectrics and stack capacitor films is presented. The method uses a contacting Elastic Material Probe (EM‐Probe) that is made of a semiconductor compatible material and forms a gate contact diameter of about 30 to 50 microns. Key electrical parameters that are measured are, Capacitive Effective Thickness (CET), Equivalent Oxide Thickness (EOT), Interface Trap Density (Dit), delta VFB Hysteresis (ΔVFB), leakage current density (JLK), Field‐to‐breakdown (FBD), Charge‐to‐breakdown (QBD) and Stress Induced Leakage Current (SILC). Measurements can be made on either blanket or in scribe line test areas in patterned wafers.

Dopant Activation and Profile Determination with an Elastic Material Probe (EM‐Probe)

In this paper, a new method is described for determining the near surface electrically active dopant density (NSURF). This is a powerful new method that allows for the monitoring of Activation for USJ Structures. The technique uses a non‐penetrating, non‐damaging probe that elastically deforms to form a contact on the bare or native oxide covered surfaces of USJ structures. Advanced Capacitance‐Voltage (CV) methods are used to determine the electrically active dopant, not carrier, density. The technique and physics will be described in detail along with several case studies.

Direct Monitoring of EOT‐JLEAK Characteristics for SiON and High‐k Gate Dielectrics

A new FEOL metrology technique based on the use of elastic material probes (EM‐Probes) is demonstrated for gate dielectric process development and monitoring for the 45 nm technology node and beyond. It is shown that critical gate dielectric electrical parameters such as Equivalent Oxide Thickness (EOT), Gate Leakage Current Density (JLEAK), and Stress Induced Leakage Current (SILC) can be accurately measured in a non‐damaging, non‐contaminating fashion on product wafers. Correlations to final device parameters are discussed which are better than any other method available.

Determination of Ultra‐shallow Junction (USJ) Quality with an Elastic Material Probe (EM‐Probe)

The formation of Ultra‐Shallow Junctions (USJ) for Source‐Drain extension regions is critical to device performance for current and future generation IC technology. Multiple process steps are involved in their formation: which can include pre‐amorphization, ion implantation and anneal. Even strained silicon and SiGe are used as materials to form USJs. The primary goal is to achieve low sheet resistances with shallow junction depths. Sheet resistance alone is not enough to properly qualify the junction. It is also important to ensure that the junctions formed are of high quality. In this paper, we explore several methods that can be used to assess the quality of pn junctions formed by USJ processes.