Steven Hung

High-k/metal gate stacks in gate first and replacement gate schemes

In this work, representative high-k/metal gate MOS-capacitor stacks were fabricated in both gate first and replacement gate integration schemes. Aluminum- and lanthanum- based cap layers (both widely accepted as Vt tuning cap layers in the industry), in addition to TiN metal gate, can tune the effective workfunction towards PMOS and NMOS, respectively. Varying Ti:N stoichiometry in TiN can induce >250mV change in TiN workfunction. 1 volt separation between NMOS and PMOS was achieved by screening various workfunction materials in replacement gate scheme. Substrate modification during the growth of aluminum was key to achieving void-free aluminum gap fill in narrow gate trenches.

Effect of composition and chemical bonding on the band gap and band offsets to Si of HfxSi1-xO2 (N) films

The energy band gap, alignment with Si and the chemical bonding of 3–4 nm thick HfxSi1−xO2 films with 0≤x≤1 were investigated as a function of composition. Nitrogen was introduced by N plasma incorporation into HfxSi1−xO2 films with x=0.3, 0.5, and 0.7 grown on a SiO2/Si stack by metal-organic chemical vapor deposition. The structure of the dielectric films was characterized by high resolution transmission electron microscopy. X-ray photoelectron spectroscopy was used to determine the band gap, as well as the energy band alignment with Si and the chemical structure of the films. The amount of Si in the films and the incorporated N were found to influence the band gap and the band alignment with Si. The band gap was found to gradually decrease with the increase in Hf content, from a value of 8.9 eV (for pure SiO2) to a value of 5.3 eV (for pure HfO2). These changes were accompanied by a reduction of the valance band offset relative to the Si substrate, from a value of 4.8 eV (for pure SiO2) to a value of 1...

Ultrathin SiO 2 interface layer growth

A variety of processes based on radical oxidation (N2O/H2) and spike RTO are investigated in this study to grow ultrathin SiO2 layers. Their process space is mapped out to cover regimes of interest for gate-last or gate-first integration of high k dielectrics with metal gates. Applieds Centura RTP chamber is found to be readily compatible with the requirements associated with 22/20nm CMOS technology.

Gate-first TiAlN P-gate electrode for cost effective high-k metal gate implementation

Gate-first (GF) high-k metal gate (HKMG) for LSTP/LOP logic and DRAM periphery applications requires an efficient and low-cost effective work function (eWF) solution. We demonstrated TiAlN for pFET eWF tuning without appreciable EOT, Jg, and interface degradation. Hence TiAlN is shown to be a key enabler to realize process-friendly and cost-effective GF HKMG implementation.

Novel metal gates for high κ applications

The development of gate systems suitable for high κ dielectrics is critical to the advancement of complementary metal-oxide-semiconductor (CMOS) devices. Both the effective work function and material stability are key parameters to these systems. A systematic study of metal gates of the composition HfxSi1-x (0.25 ≤ x ≤ 1) is demonstrated here, including XPS, XRD and four point probe measurements. The effective work function of each material is evaluated and it is shown that it can be tuned from 4.5 to less than 4.0 eV. Suitable work functions for n-channel metal-oxide-semiconductor applications (4.05 ± 0.2 eV) were achieved using hafnium rich compositions; however, XPS and diffraction measurements confirmed that these materials demonstrated a high propensity to oxidise, causing the reduction of the underlying oxides, making them unsuitable for commercial application.

A novel high-k gate dielectric HfLaO for next generation CMOS technology

The physical and electrical characteristics of high-k (HK) gate dielectric HfLaO were systematically investigated. Incorporation of La in HfO2 can raise the film crystallization temperature from 400degC to 900degC. Moreover, NMOSFETs fabricated with HfLaO gate dielectric exhibit superior electrical performances in terms of threshold voltage (Vth), bias temperature instability (BTI), channel electron mobility and gate leakage current compared to those fabricated with HfO2 dielectric. Particularly, the authors also report that the effective work function (EWF) of metal gate (MG) can be tuned to a wide enough range to fulfil the requirement of bulk CMOSFETs by employing HfLaO dielectric and n- and p-type metal gates respectively. These advantages are correlated to the enhanced thermal stability and reduction of oxygen vacancy density in HfLaO compared to HfO2, making it a promising high-k gate dielectric to replace SiO2 and SiON to meet the ITRS requirements. Finally, a possible dual metal gate CMOS integration process is proposed

Replacement metal gate extendible to 11 nm technology

This paper describes novel Co-Al metal fill capable of filling sub-10nm trenches. Co-Al fill shows advantages in threshold voltage (VTH) variation. The conductivity of the fill was evaluated using a Co-Al alloy conductance model. By demonstrating better VTH variability, superior conductivity and gap fill, Co-Al shows extendibility to the 11nm metal gate and beyond.

Trends in gate stack engineering

MOSFET scaling requires an increase in the dielectric capacitance and hence a decrease in the dielectric electrical thickness. In this paper, we review the scaling trends for the gate dielectric and the gate electrode as the industry faces the challenges of introducing new materials into production.

Enabling thermal IL and ALD HfOx integration for sub-20nm gate stack

World class EOT scaling and reliability performance has been achieved by integration (no air-break) of thermal interface layer (IL) and ALD high-k. RTP process is used for the formation of Ultra-Thin IL (UT-IL) and Mono-Layer IL (ML-IL). While integrated with ALD HfOx process, the resultant dielectric stack can reach 6Å EOT with excellent gate leakage, mobility and BTI reliability performances. The experiment also demonstrates that integrated thermal IL/HfOx stack provides lower pre-existing trap density and lower trap generation during BTI when compared to conventional chemical oxide IL/air-beak/HfOx stack.

High-k Gate Stack: Improved Reliability through Process Clustering

Introduction High-k (HK) gate dielectric stack process integration is one of the most critical and challenging steps in the fabrication of CMOS since its adoption at the 45nm node [1]. A typical HK stack consists of the SiO2 interfacial layer (iL) followed by a nitrided and annealed HK dielectric. Both the nitridation and anneal results in an increased dielectric constant and improved HK and stability. It has been demonstrated in numerous papers that the quality of the HK bulk material and the interface with the iL plays a critical role in transistor’s reliability degradation. This degradation, generally due to electron trapping in the HK bulk and/or at the iL/HK interface, is quantified by Bias-Temperature Instability (BTI) which closely correlates to CV hysteresis [2]. Because of such reliability degradation concerns, clustering of the different HK stack process chambers in one single tool is critical in eliminating layer exposure to fab ambient that could result in HK bulk and interface quality degradation.