William L. Martino

A 4-Mb 0.18-/spl mu/m 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers

A 4-Mb toggle MRAM, built in 0.18-/spl mu/m five level metal CMOS technology, uses a 1.55 /spl mu/m/sup 2/ bit cell with a single toggling magneto tunnel junction to achieve a chip size of 4.5 mm /spl times/ 6.3 mm. The memory uses unidirectional programming currents controlled by locally mirrored write drivers to apply a robust toggle write sequence. An isolated read architecture driven by a balanced three input current mirror sense amplifier supports 25-ns cycle time asynchronous operation.

An on-chip back-bias generator for MOS dynamic memory

An on-chip back-bias generator for 64K dynamic MOS RAM has been developed.The use of this generator achieves the goal of a single 5 V power supply part while preserving the advantages of substrate bias in n-channel MOS technology. These advantages include the elimination of substrate injection current from localized forward biasing of diodes, improved speed and power characteristics, and a larger differential data signal on the bit sense lines. The generator circuit avoids several pit-falls on on-chip V/SUB BB/ generation. The circuit pumps to a known regulated voltage. This avoids substrate drift with changes in substrate current resulting from changes in cycle time. This drift will change device characteristics and degrade storage levels. A unique two-level reference scheme avoids changes in substrate bias voltage that otherwise result from the shift in V/SUB BB/ between precharged and active memory states when memory duty cycle changes. The standby power used by the generator is only 0.74 mW.

A 180 Kbit Embeddable MRAM Memory Module

180 Kbit magnetoresistive random access memory (MRAM) designed for embedding in a 0.28 micron CMOS process has been developed. The memory cell is based on a 1-transistor 1-magnetic tunnel junction (1T1MTJ) bit cell. The architecture, write driver, and sense amplifier are described. The use of a test register to characterize and optimize the memory design is also discussed.

A 4Mb 0.18 /spl mu/m 1T1MTJ Toggle MRAM memory

The 4.5/spl times/6.3mm/sup 2/ 25ns cycle-time 4Mb Toggle MRAM memory, built in 0.18 /spl mu/m 5M CMOS technology, uses a 1.55 /spl mu/m/sup 2/ bit cell with a single toggling magneto tunnel junction. The memory uses uni-directional programming currents with isolated write and read paths and balanced current mirror sense amplifier.