Thomas Andre

A 4-Mb 0.18-/spl mu/m 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers

A 4-Mb toggle MRAM, built in 0.18-/spl mu/m five level metal CMOS technology, uses a 1.55 /spl mu/m/sup 2/ bit cell with a single toggling magneto tunnel junction to achieve a chip size of 4.5 mm /spl times/ 6.3 mm. The memory uses unidirectional programming currents controlled by locally mirrored write drivers to apply a robust toggle write sequence. An isolated read architecture driven by a balanced three input current mirror sense amplifier supports 25-ns cycle time asynchronous operation.

ST-MRAM fundamentals, challenges, and applications

Magnetoresistive Random Access Memory (MRAM) technology emerged from research and development into volume production within the last decade in the form of Toggle MRAM. The latest Magnetic Tunnel Junction (MTJ) based memory technology, Spin-Torque MRAM, has reached the level of customer sampling, offering higher density and bandwidth. Spin-Torque MRAM enables new applications, offers a wide range of features for use in embedded memory, and has the potential to extend to technology nodes beyond the capability of DRAM. This paper describes the devices, fundamental circuit challenges, and applications of this evolving MTJ based memory.

A 180 Kbit Embeddable MRAM Memory Module

180 Kbit magnetoresistive random access memory (MRAM) designed for embedding in a 0.28 micron CMOS process has been developed. The memory cell is based on a 1-transistor 1-magnetic tunnel junction (1T1MTJ) bit cell. The architecture, write driver, and sense amplifier are described. The use of a test register to characterize and optimize the memory design is also discussed.