Halbert S. Lin

A 4-Mb 0.18-/spl mu/m 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers

A 4-Mb toggle MRAM, built in 0.18-/spl mu/m five level metal CMOS technology, uses a 1.55 /spl mu/m/sup 2/ bit cell with a single toggling magneto tunnel junction to achieve a chip size of 4.5 mm /spl times/ 6.3 mm. The memory uses unidirectional programming currents controlled by locally mirrored write drivers to apply a robust toggle write sequence. An isolated read architecture driven by a balanced three input current mirror sense amplifier supports 25-ns cycle time asynchronous operation.

ST-MRAM Fundamentals, Challenges, and Outlook

Magnetoresistive Random Access Memory (MRAM) technology was introduced into the market last decade in the form of Toggle MRAM, available in densities up to 16Mb. In the last few years, Spin-Torque MRAM, the next generation of Magnetic Tunnel Junction (MTJ) based memory, has become available offering higher density and bandwidth. This paper describes the device and design fundamentals, the associated challenges, and the outlook of this evolving MTJ based memory.