Wipakorn Jevasuwan

1-nm-capacitance-equivalent-thickness HfO2/Al2O3/InGaAs metal-oxide-semiconductor structure with low interface trap density and low gate leakage current density

We have studied the impact of the Al2O3 inter-layer on interface properties of HfO2/InGaAs metal-oxide-semiconductor (MOS) interfaces. We have found that the insertion of the ultrathin Al2O3 inter-layer (2 cycle: 0.2 nm) can effectively improve the HfO2/InGaAs interface properties. The frequency dispersion and the stretch-out of C-V characteristics are improved, and the interface trap density (Dit) value is significantly decreased by the 2 cycle Al2O3 inter-layer. Finally, we have demonstrated the 1-nm-thick capacitance equivalent thickness in the HfO2/Al2O3/InGaAs MOS capacitors with good interface properties and low gate leakage of 2.4 × 10−2 A/cm2.

Impact of Fermi level pinning inside conduction band on electron mobility of In x Ga 1−x As MOSFETs and mobility enhancement by pinning modulation

We clarified that Fermi levels at InGaAs MOS interfaces are pinned inside conduction band (CB) and that this pinning severely degrades the effective mobility. Also, the energy position of the Fermi level pinning (FLP) is found to be tunable. It is experimentally shown that the increase in the difference between the FLP position and the CB minimum (CBM) leads to high mobility at high Ns region. Also, possible physical origin for this FLP is proposed.

Tensile-Strained GeSn Metal–Oxide–Semiconductor Field-Effect Transistor Devices on Si(111) Using Solid Phase Epitaxy

We demonstrate tensile-strained GeSn metal–oxide–semiconductor field-effect transistor (MOSFET) devices on Si(111) substrates using solid phase epitaxy of amorphous GeSn layers. Amorphous GeSn layers are obtained by limiting the adatom surface mobility during deposition. Subsequent annealing transforms the amorphous layer into single-crystalline GeSn by solid phase epitaxy. Single-crystalline GeSn layers with 4.5% Sn and 0.33% tensile strain are fabricated on Si(111) substrates. To verify the structural quality of thin-film GeSn as a channel material, we fabricate ultrathin GeSn p-channel MOSFETs (pMOSFETs) on Si(111). We demonstrate junctionless depletion-mode operation of tensile-strained GeSn(111) pMOSFETs on Si substrates.

Impact of Fermi level pinning inside conduction band on electron mobility in InGaAs metal-oxide-semiconductor field-effect transistors

Combining the split capacitance-voltage method with Hall measurements revealed the existence of interface traps within the conduction band (CB) of InGaAs in metal-oxide-semiconductor (MOS) structures with Al2O3 (or HfO2)/InGaAs interfaces. The impact of these interface traps on inversion-layer mobilities in InGaAs MOS field-effect transistors with various interface structures was investigated. We found that the interface traps (>1013 cm−2 eV−1) induce Fermi level pining at an energy level 0.21–0.35 eV above the CB minimum, which degrades the mobilities in the high inversion carrier concentration region. Furthermore, the energy levels are tunable by changing the interface structures.

Self-limiting growth of ultrathin Ga2O3 for the passivation of Al2O3/InGaAs interfaces

Ga2O3 film growth on InGaAs substrates was investigated using an atomic layer deposition system with trimethylgallium (TMGa) and H2O as precursors. Self-limiting growth of Ga2O3 was confirmed on InGaAs substrates as well as on Si and GaAs. During initial formation of the Ga2O3 film on an InGaAs substrate, the selective self-cleaning effect of TMGa on AsOx and GaOx was observed. The insertion of ultrathin Ga2O3 into an Al2O3/InGaAs gate stack as an interfacial passivation layer proved quite effective to reduce Dit around the midgap. The Al2O3/InGaAs MISFET performance also revealed improvement of the effective mobility for both NH4OH- and (NH4)2S-treated devices.

Initial Processes of Atomic Layer Deposition of Al2O3 on InGaAs: Interface Formation Mechanisms and Impact on Metal-Insulator-Semiconductor Device Performance

Interface-formation processes in atomic layer deposition (ALD) of Al2O3 on InGaAs surfaces were investigated using on-line Auger electron spectroscopy. Al2O3 ALD was carried out by repeating a cycle of Al(CH3)3 (trimethylaluminum, TMA) adsorption and oxidation by H2O. The first two ALD cycles increased the Al KLL signal, whereas they did not increase the O KLL signal. Al2O3 bulk-film growth started from the third cycle. These observations indicated that the Al2O3/InGaAs interface was formed by reduction of the surface oxides with TMA. In order to investigate the effect of surface-oxide reduction on metal-insulator-semiconductor (MIS) properties, capacitors and field-effect transistors (FETs) were fabricated by changing the TMA dosage during the interface formation stage. The frequency dispersion of the capacitance-voltage characteristics was reduced by employing a high TMA dosage. The high TMA dosage, however, induced fixed negative charges at the MIS interface and degraded channel mobility.

High electron mobility triangular InGaAs-OI nMOSFETs with (111)B side surfaces formed by MOVPE growth on narrow fin structures

Triangular In_0.53Ga_0.47As-OI nMOSFETs with smooth (111)B side surfaces on Si have been successfully fabricated. Triangular shaped channels with bottom width down to 30 nm were formed by MOVPE growth on narrow InGaAs-OI fins. The formed (111)B surface was demonstrated to provide higher mobility compared with reference InGaAs-OI tri-gate (1.9×) as well as bulk (100) InGaAs nMOSFETs (1.6×), which is possibly due to reduced D_it in conduction band and resultant suppressed carrier trapping at the MOS interface. Lower noise and hysteresis in triangular device supported this model. High I_on value of 930 μA/μm at L_g = 300 nm indicates the potential of the triangular InGaAs-OI nMOSFETs for ultra-low power and high performance CMOS applications.

High mobility p-n junction-less InGaAs-OI tri-gate nMOSFETs with metal source/drain for ultra-low-power CMOS applications

We have successfully fabricated InGaAs-OI tri-gate nMOSFETs, for the first time. The devices were depletion-type (p-n junction-less) nFETs with Fin-channel width (W_fin) down to 20 nm and had metal source/drain structures. It was experimentally demonstrated that W_fin scaling effectively improved cut-off properties at N_d up to 5 × 10¹⁸ cm^-3 and the electron mobility in the narrowest channel (W_fin = 20 nm) was about 3x higher than that of the inversion layer. It was also demonstrated that enhancement of In content from 53% to 70% leaded to 30% I_on enhancement without I_off degradation.

Ultrathin GeSn p-channel MOSFETs grown directly on Si(111) substrate using solid phase epitaxy

Ultrathin GeSn layers with a thickness of 5.5 nm are fabricated on a Si(111) substrate by solid phase epitaxy (SPE) of amorphous GeSn layers with Sn concentrations up to 6.7%. We demonstrate well-behaved depletion-mode operation of GeSn p-channel metal–oxide–semiconductor field-effect transistors (pMOSFETs) with an on/off ratio of more than 1000 owing to the ultrathin GeSn channel layer (5.5 nm). It is found that the on current increases significantly with increasing Sn concentration at the same gate overdrive, attributed to an increasing substitutional Sn incorporation in Ge. The GeSn (6.7%) layer sample shows approximately 90% enhancement in hole mobility in comparison with a pure Ge channel on Si.

Metal-catalyzed electroless etching and nanoimprinting silicon nanowire-based solar cells: Silicon nanowire defect reduction and efficiency enhancement by two-step H2 annealing

The effects of H2 annealing on material properties including defects of silicon nanowire (SiNW) surface and Si film layer for solar cell application were investigated. Single-junction solar cells consisting of n-SiNWs and chemical vapor deposition grown p-Si matrix were demonstrated using two-step H2 annealing. n-SiNWs formed by two different methods of metal-catalyzed electroless etching and nanoimprinting followed by the Bosch process were compared. Two-step H2 annealing at 900 °C for 10 min after both n-SiNW formations and subsequent p-Si matrix deposition effectively improved SiNW surface and p-Si crystallinity, resulting in higher solar cell efficiency.