Minoru Oda

High-mobility and low-parasitic resistance characteristics in strained Ge nanowire pMOSFETs with metal source/drain structure formed by doping-free processes

Metal source/drain (S/D) Ge nanowire MOSFETs with a compressive strain as high as 3.8% were fabricated by the 2-step Ge-condensation technique without intentional doping for the S/D. Record high inversion hole mobility (μ_eff = 855 cm²/Vs @ N_s = 5×10¹²cm^-2) and saturation drain current 731μA/μm at V_d=-1V were achieved among Ge nanowire pFETs ever reported. It is found that the extremely low contact resistivity ρ_c ~ 4×10^-8O cm² for the Schottky contact contributes to the high saturation current as well as the high mobility.

Self-limiting growth of ultrathin Ga2O3 for the passivation of Al2O3/InGaAs interfaces

Ga2O3 film growth on InGaAs substrates was investigated using an atomic layer deposition system with trimethylgallium (TMGa) and H2O as precursors. Self-limiting growth of Ga2O3 was confirmed on InGaAs substrates as well as on Si and GaAs. During initial formation of the Ga2O3 film on an InGaAs substrate, the selective self-cleaning effect of TMGa on AsOx and GaOx was observed. The insertion of ultrathin Ga2O3 into an Al2O3/InGaAs gate stack as an interfacial passivation layer proved quite effective to reduce Dit around the midgap. The Al2O3/InGaAs MISFET performance also revealed improvement of the effective mobility for both NH4OH- and (NH4)2S-treated devices.

Demonstration of ultimate CMOS based on 3D stacked InGaAs-OI/SGOI wire channel MOSFETs with independent back gate

An ultimate CMOS structure composed of high mobility wire channel InGaAs-OI nMOSFETs and SGOI pMOSFETs has been successfully fabricated by means of sequential 3D integration. Well behaved CMOS inverters and first demonstration of InGaAs/SiGe (Ge) dual channel CMOS ring oscillators are reported. The 21-stage CMOS ring oscillator operation was achieved at Vdd as low as 0.37 V with the help of adaptive back gate bias, VBG control.

Hole-Mobility and Drive-Current Enhancement in Ge-Rich Strained Silicon-Germanium Wire Tri-Gate Metal-Oxide-Semiconductor Field-Effect Transistors with Nickel-Germanosilicide Metal Source and Drain

on such Ge-rich non-planar channels. 9) In this letter, we demonstrate a fabrication process and high hole mobility characteristic of uniaxially strained SiGe-on-insulator (SGOI) channel tri-gate MOSFET with Ge fraction x of 0.65 formed by two-step Ge condensation. The current drive of a uniaxially strained SGOI channel tri-gate MOSFET, which has a nickel-germanosilicide (NiSiGe) metal S/D structure with gate length (Lg) of 50 nm and wire width (Wwire) of 25 nm, was also investigated and compared with that of SOI channel tri-gate MOSFETs. Sufficiently high mobility and higher current drive were obtained in the SGOI channel tri-gate FETs than those of the SOI channel tri-gate MOSFET, as well as high immunity to the short-channel effects.

High electron mobility triangular InGaAs-OI nMOSFETs with (111)B side surfaces formed by MOVPE growth on narrow fin structures

Triangular In_0.53Ga_0.47As-OI nMOSFETs with smooth (111)B side surfaces on Si have been successfully fabricated. Triangular shaped channels with bottom width down to 30 nm were formed by MOVPE growth on narrow InGaAs-OI fins. The formed (111)B surface was demonstrated to provide higher mobility compared with reference InGaAs-OI tri-gate (1.9×) as well as bulk (100) InGaAs nMOSFETs (1.6×), which is possibly due to reduced D_it in conduction band and resultant suppressed carrier trapping at the MOS interface. Lower noise and hysteresis in triangular device supported this model. High I_on value of 930 μA/μm at L_g = 300 nm indicates the potential of the triangular InGaAs-OI nMOSFETs for ultra-low power and high performance CMOS applications.

High mobility p-n junction-less InGaAs-OI tri-gate nMOSFETs with metal source/drain for ultra-low-power CMOS applications

We have successfully fabricated InGaAs-OI tri-gate nMOSFETs, for the first time. The devices were depletion-type (p-n junction-less) nFETs with Fin-channel width (W_fin) down to 20 nm and had metal source/drain structures. It was experimentally demonstrated that W_fin scaling effectively improved cut-off properties at N_d up to 5 × 10¹⁸ cm^-3 and the electron mobility in the narrowest channel (W_fin = 20 nm) was about 3x higher than that of the inversion layer. It was also demonstrated that enhancement of In content from 53% to 70% leaded to 30% I_on enhancement without I_off degradation.

Advantage of (001)/ oriented channels in biaxially- and uniaxially strained-Ge-on-insulator pMOSFETs with NiGe metal source/drain

We compared current drivability between (001)/<;100> and (001)/<;110> strained Ge-on-insulator pMOSFETs under biaxial and uniaxial stress. Higher intrinsic transconductance (gm, int) was experimentally demonstrated for the first time in the (001)/<;100> devices with a gate length (Lg) less than 100 nm under the both strain conditions, although this is not the case for the long-channel devices. This is possibly attributable to more significant non-parabolicity of the valence band (VB) dispersion, i.e., heavier effective mass at energy apart from the VB minimum, along <;110> than along <;100>. It is also found that the parasitic resistance (RSD) governed by the contact resistance between the NiGe-source and the strained-Ge channel is lower along <;100> direction than the counterpart. As a result, higher drive current was observed for a <;100> device with Lg of 55 nm under both the biaxial-(644 μA/μm) and uniaxial stress (536 μA/μm) at Vd = -0.5 V than for <;110> counterpart, although mobility was highest in the <;110> channel under the uniaxial stress.

3D integration of high mobility InGaAs nFETs and Ge pFETs for ultra low power and high performance CMOS

InGaAs/Ge stacked 3D CMOS inverters have been successfully demonstrated down to Vdd = 0.2 V. The negligible degradation of the top and the bottom device characteristics indicates high technical feasibility of the InGaAs/Ge stacked 3D integration for ultra low-power and high performance CMOS.

Fabrication of Bonded GeOI Substrates with Thin Al2O3/SiO2 Buried Oxide Layers

Thin-body GeOI substrates with thin Al2O3/SiO2 BOX layers are successfully fabricated for the first time. It is found that the bonding interface was robust enough for Mechanical Polishing and CMP even after bonding at a room temperature in atmosphere. The GeOI surfaces etched with ozone water are atomically flat. Moreover, Dit of as low as 3.9e+11 eV-1cm-2 at the GeOI/BOX is obtained. These results suggest that negligible negative impact on carrier mobility and sub-threshold characteristics can be realized by using the GeOI substrates with thin Al2O3/SiO2 BOX layers.

0.8nm EOT and High Hole Mobility of Ge P-MISFETs Using HfAlO/GeOx/Ge Gate Stacks Formed by Plasma Oxidation and Atomic Layer Deposition

In conclusion, HfAlO/GeOx/Ge p-MISFETs with EOT of 0.84nm are demonstrated. Low interface trap density of GeOx/Ge interface enable us to high mobility. Careful control of high-k fixed charges will allow achieving low EOT and high mobility of Ge p-MISFETs.