Andy Strachan

Hot carrier reliability of N-LDMOS transistor arrays for power BiCMOS applications

This paper evaluates the hot carrier performance of n-channel lateral DMOS (N-LDMOS) transistors. The N-LDMOS has been the common choice for the driver transistor in high voltage (20-30 V) smart power applications. These high drain voltages potentially make N-LDMOS hot carrier degradation an important reliability concern. This paper focuses on the hot carrier test methodology and geometry effects in N-LDMOS transistor arrays. This paper differs from previous work in that it describes for the first time the HC performance of N-LDMOS transistor arrays rather than discrete devices and discusses an N-LDMOS failure mode not yet addressed in the literature.

A trench-isolated power BiCMOS process with complementary high performance vertical bipolars

A new process for mixed-signal and power management applications is introduced. The process architecture is designed to achieve high V/sub A/, high f/sub T/ complementary 24 V bipolar devices coupled to 0.5 /spl mu/m CMOS and 24 V power MOS. For optimum performance and die size the process uses 1 /spl mu/m wide poly-filled trench isolation.

Monolithic integration of trench vertical DMOS (VDMOS) power transistors into a BCD process

The monolithic integration of trench vertical DMOS (VDMOS) n-channel transistors into an IC BCD process is reported for the first time. The integration scheme for the trench VDMOS module is discussed and silicon results are compared with TCAD simulations. For a 50-V device, the integrated trench device is shown to offer at least a factor-of-two R/sub DS(ON)/ /spl times/ area advantage over its planar counterpart. An R/sub DS(ON)/ /spl times/ area value of 80 m/spl Omega/mm/sup 2/ is achieved for the integrated trench VDMOS using a minimum feature size of 1 /spl mu/m.

Optimization of LDMOS array design for SOA and hot carrier lifetime

Optimization of LDMOS devices to meet safe operating area (SOA) and hot carrier lifetime targets is a current challenge for process development. This work focuses on novel results in the use of layout techniques and cell design to improve both SOA and hot carrier reliability of LDMOS arrays. Specific improvements to cell based array layouts that increase SOA and hot carrier lifetime for fixed transistor architecture are reported.

Design optimization of N-LDMOS transistor arrays for hot carrier lifetime enhancement

Todays power management devices often require operation in the 20-30 V range. These applications combine a high performance BiCMOS process with a power lateral n-channel DMOS (N-LDMOS) driver. To obtain high drive currents and low on-resistance, LDMOS devices are often implemented in transistor arrays. Because of the high voltages and currents applied to these arrays, hot carrier (HC) degradation is a real reliability concern. This paper differs from previous work in that it discusses for the first time one- and two-dimensional aspects of LDMOS transistor array layout on HC performance and introduces a novel LDMOS transistor layout featuring a drain ring that substantially improves the arrays HC performance.

1-D and 2-D hot carrier layout optimization of N-LDMOS transistor arrays

Todays power management devices often require operation in the 20-30 V range. These applications often combine a high performance BiCMOS process with a power lateral DMOS (LDMOS) driver. To obtain high drive current density and minimal on-resistance (Rdson), LDMOS devices are often implemented in transistor arrays. Because of the high voltages and currents applied to these LDMOS arrays hot carrier (HC) degradation is a real reliability concern. This paper focuses on improving the HC reliability of N-LDMOS transistor arrays. Layout optimization is emphasized since the LDMOS and Bipolar/CMOS devices share common process steps. This paper differs from previous work in that it discusses for the first time the one- and two-dimensional aspects of LDMOS transistor array layout on HC performance. In addition this paper introduces for the first time a novel LDMOS transistor layout featuring a Drain Ring that dramatically improves the HC performance of these arrays.

Substrate Current Injection and Latchup in Complementary Vertical Bipolar Processes

Challenges and solutions for substrate current injection and latchup phenomena in complementary BiCMOS technologies are described. The vertical PNP presents specific challenges that differ from CMOS or NPN-only BiCMOS cases

Hot-carrier reliability and design of N-LDMOS transistor arrays

The increase in handheld and portable appliances operating in the 20-30 V range have driven the need for IC power management control devices. These circuits combine high performance CMOS and bipolar transistors with a power MOS driver. The n-channel lateral DMOS (N-LDMOS) is a common choice for the driver transistor. Because of high drain voltages used by LDMOS devices hot-carrier degradation is an important reliability concern. This paper focuses on the N-LDMOS hot-carrier test methodology, degradation mechanism and effect of device layout on N-LDMOS hot-carrier performance. This paper differs from previous work in that it describes an N-LDMOS hot-carrier failure mode not yet addressed in the literature and for the first time describes the hot-carrier performance of transistor arrays rather than discrete devices.

Simultaneous Extraction of Collector and Substrate Series Resistance by Simple DC Measurement

A new forced emitter current method is proposed for the simultaneous measurement of collector and substrate series resistance in bipolar transistors. Compared with conventional series resistance extraction method, this new method does not need any prior knowledge of certain device parameters, or any pre-selected bias condition. It can be used for any bulk bipolar technology

Impact of buried layer processing on gate oxide integrity [CMOS processing]

Buried layers are used in bipolar devices to lower collector resistance in bulk silicon and SOI (silicon-on-insulator) technologies. They are also used with deep trench for isolating different devices types. This work investigates the effect of buried layer processing on CMOS capacitor reliability, comparing results between bulk silicon and SOI substrates. Opposing results from bulk and SOI technologies indicate different degradation mechanisms at play. The SOI starting material requires that metal contaminant gettering be taken in to account in the processing of the buried layers.