Wolfgang Hoenlein

Sub-20 nm short channel carbon nanotube transistors.

Carbon nanotube field-effect transistors with sub-20 nm long channels and on/off current ratios of >10(6) are demonstrated. Individual single-walled carbon nanotubes with diameters ranging from 0.7 to 1.1 nm grown from structured catalytic islands using chemical vapor deposition at 700 degrees C form the channels. Electron beam lithography and a combination of HSQ, calix[6]arene, and PMMA e-beam resists were used to structure the short channels and source and drain regions. The nanotube transistors display on-currents in excess of 15 microA for drain-source biases of only 0.4 V.

Electrochemical functionalization of multi-walled carbon nanotubes for solvation and purification

Abstract The chemical modification of multi-walled carbon nanotubes using electrolysis is described. It is found that the evolution of the halogens chlorine or bromine on an anode made from a foil of carbon nanotubes couples halogen atoms to the nanotube lattice. Furthermore, oxygen bearing functional groups, such as hydroxyl and carboxyl groups, are formed at the same time aiding solvation of the nanotubes in water or alcohol without any surfactant. Impurities and low grade modified nanotubes remain insoluble. The halogenated carbon nanotubes can be converted with sodium amide or triphenylmethyllithium to add the corresponding functional groups.

Bias dependence and electrical breakdown of small diameter single-walled carbon nanotubes

The electronic breakdown and the bias dependence of the conductance have been investigated for a large number of catalytic chemical vapor deposition grown single-walled carbon nanotubes (SWCNTs) with very small diameters. The convenient fabrication of thousands of properly contacted SWCNTs was possible by growth on electrode structures and subsequent electroless palladium deposition. Almost all of the measured SWCNTs showed at least weak gate dependence at room temperature. Large differences in the conductance and breakdown behavior have been found for “normal” semiconducting SWCNTs and small band-gap semiconducting SWCNTs.

Large-scale integration of carbon nanotubes into silicon-based microelectronics

The integration of carbon nanotubes (CNTs) into conventional silicon-technology with potential applications as interconnects, transistors, memory-cells, and sensors is an promising goal. Theoretical and experimental results indicate that CNT-based devices can outperform conventional silicon microelectronics. Concepts for the creation of vertical interconnects and transistors made out of CNTs, which allow a large scale integration, are presented. A vital step for their realization is the synthesis of individual CNTs with controlled diameters at lithographically predefined locations. Employing catalyst mediated Chemical Vapor Deposition (CVD) isolated CNTs have been grown out of holes in silicon dioxide which have been created by optical lithography. This allows the precise placement of individual CNTs on silicon substrates. Furthermore, the diameter of each CNT adjusts to the hole size, which makes it possible to control this important property separately for individual CNTs. In combination with the vertical integration concept those findings constitute a milestone in the parallel manufacture of nanotube-based devices with scalable batch processes.

Carbon Nanotubes: Can they become a microelectronics technology?

Carbon nanotubes (CNTs) have a large variety of properties that make them attractive for applications in microelectronics. A comparison of carbon nanotube field‐effect transistors with silicon MOSFETs shows that CNT devices outperform state‐of‐the‐art silicon transistors. A silicon technology review gives the benchmark for an assessment of the current CNT technology and identifies the growth and placement procedures that are not yet sufficient for industrial applications. Finally, the vertical CNT transistor concept is introduced which deals with the technological problems and opens a new route for 3D integration.

Catalytic CVD of SWCNTs at Low Temperatures and SWCNT Devices

New results on the planar growth of single‐walled carbon nanotubes (SWCNTs) by catalytic chemical vapor deposition (CVD) at low temperatures will be reported. Optimizing catalyst, catalyst support, and growth parameters yields SWCNTs at temperatures as low as 600 °C. Growth at such low temperatures largely affects the diameter distribution since coalescence of the catalyst is suppressed. A phenomenological growth model will be suggested for CVD growth at low temperatures. The model takes into account surface diffusion and is an alternative to the bulk diffusion based vapor‐liquid‐solid (VLS) model. Furthermore, carbon nanotubes field effect transistors based on substrate grown SWCNTs will be presented. In these devices good contact resistances could be achieved by electroless metal deposition or metal evaporation of the contacts.

Self‐Aligned Contacting of Carbon Nanotubes

An important prerequisite for the implementation of carbon nanotubes (CNTs) in microelectronic circuits is the evaluation of their electronic properties. For this, the generation of low‐ohmic electrical contacts between CNTs and metallic circuit lines is crucial. We describe a parallel process which does not rely on e‐beam lithography and yields self‐aligned, low‐ohmic contacts on wafer scale. CNTs that are spray deposited on metallic test structures created by optical lithography are subsequently embedded by electroless metallization and annealed. With this method we are able to simultaneously lower the contact resistance of an unlimited number of CNTs. The reduction of the contact resistance depends on the metals involved and the annealing process. This new method enables the statistical evaluation of the CNT quality dependence on synthesis conditions.

A nonvolatile single ferro fet memory concept with disturbance free operation scheme

Abstract A novel AND-type ferroelectric field effect transistor memory concept for solid state mass storage applications is described. Disturbance problems caused by disturbance pulses between adjacent memory cells are prevented by device improvements and by choosing appropriate programming and read voltages. The memory array presented here uses global source lines each of which is connected to its own sense amplifier. Disturbance free and fully functional operation of the memory concept has been demonstrated by circuit simulations. The results of the simulations yield a data access time comparable to DRAMs.