Thomas Haneder

A digital CMOS DNA chip

A fully electronic medium density DNA micro array is presented using a CMOS process extended by gold electrodes. The chip provides 128 sensor sites, in-sensor site current-mode A/D conversion, peripheral circuitry including bandgap and current references, D/A-converters to provide electrode bias voltages, calibration circuitry, and a 6 pin interface for power supply and serial digital data transfer.

Integrated circuits for the biology-to-silicon interface

An overview is given of CMOS-based sensor and actuator chips for in-vitro applications in the biotechnology area. We address the challenges and the potential of the combination of solid-state circuits with the wet world of bio molecules and living cells. Basic biological operating principles, market considerations, extended CMOS processing issues, and concrete circuit examples are discussed.

CMOS-Based Biosensor Arrays

CMOS-based sensor array chips provide new and attractive features as compared to todays standard tools for medical, diagnostic, and biotechnical applications. Examples for molecule- and cell-based approaches and related circuit design issues are discussed.

A CMOS Medium Density DNA Microarray with Electronic Readout

A CMOS chip-based approach is reviewed for fully electronic DNA detection. The electrochemical sensor principle used, CMOS integration of the required transducer materials, chip architecture and circuit design issues are discussed, respectively. Electrochemical and biological results obtained on the basis of medium density microarray sensor CMOS chips with 16 × 8 sensor sites prove proper operation.

Relaxation effects and steady-state conduction in non-stoichiometric SBT films

Abstract The DC current response of strontium bismuth tantalate (SBT) thin films was investigated as a function of applied voltage and temperature. The transient relaxation currents have been found to obey the universal Curie-von Schweidler law independent of the previous polarization. The steady-state current is independent of the initial polarization but depends on temperature. In the mid-voltage regime the conduction is thermally activated. At high applied voltages V the leakage current depends upon V4.

Effect of Film Composition on Low Temperature Processing of SBT Deposited by MOCVD

Bi-layered ferroelectric strontium bismuth tantalate (SBT) thin films of various film compositions were deposited on Pt/Ti/SiO 2 /Si substrates by metalorganic chemical vapor deposition (MOCVD) and crystallized at 700°C in oxygen ambient. Phase transition, orientation, second phases and remanent polarization were investigated with respect to film stoichiometry. X-ray diffraction (XRD) measurements revealed that excess Bi lowers the transition temperature from fluorite-type to ferroelectric phase. However, SBT films with Bi-excess of 15% or higher exhibit pronounced Bi-loss during crystallization and a decrease in the relative intensity of the (200) peak. Highly Sr-deficient films are not fully crystallized but support pyrochlore formation. The maximum remanent polarization is obtained at a Sr-deficiency of 15–25% and a Bi-excess of 10% (0.85/2.20/2.00).

Integrated circuits for the biology-to-silicon interface [biotechnology]

An overview is given of CMOS-based sensor- and actuator chips for in-vitro applications in the biotechnology area. We address the challenges and the potential of the combination of solid-state circuits with the wet world of bio molecules and living cells. Basic biological operating principles, market considerations, extended CMOS processing issues and concrete circuit examples are discussed.

Disturb free programming scheme for single transistor ferroelectric memory arrays

Abstract Conventional AND and NOR non-volatile memory array circuits utilizing a single ferroelectric memory field effect transistor (FEMFET) cell structure were simulated by using a BSIM3v3 based FEMFET compact model. It is shown that the use of the common V pp /2 and V pp /3 rules for programming a transistor in a FEMFET cell-array may cause the loss of stored information in adjacent memory cells due to disturb pulses. To overcome this problem we propose to back-bias the substrate during the write cycle, which extends the depletion region of the FEMFET to higher gate-source voltages, and thus reduces the influence of a disturb pulse on the polarization of the gate ferroelectric. In addition we discuss device improvements which reduce the susceptibility to data loss without back-biasing the substrate in order to minimize cell area.

A nonvolatile single ferro fet memory concept with disturbance free operation scheme

Abstract A novel AND-type ferroelectric field effect transistor memory concept for solid state mass storage applications is described. Disturbance problems caused by disturbance pulses between adjacent memory cells are prevented by device improvements and by choosing appropriate programming and read voltages. The memory array presented here uses global source lines each of which is connected to its own sense amplifier. Disturbance free and fully functional operation of the memory concept has been demonstrated by circuit simulations. The results of the simulations yield a data access time comparable to DRAMs.