Manfred Engelhardt

Comprehensive study of the resistivity of copper wires with lateral dimensions of 100 nm and smaller

Copper wires were prepared in a silicon oxide matrix using the methods of semiconductor manufacturing and were electrically characterized. The width of the smallest structure was 40 nm and of the largest, 1000 nm; the heights were 50, 155, and 230 nm. Many samples of each size have been measured in order to perform a systematic investigation. The resistivity of the sample was extracted using the temperature coefficient of resistance. A significant increase in the resistivity was found for the small structures (roughly a factor 2 for 50-nm width). A model based on physical parameters was used in the analysis of the electrical data and very good agreement was obtained. The sensitivity of the various model parameters obtained by a best-fit procedure to the experimental data has been investigated. The impact of width and height on the resistivity, the influence of electron scattering at grain boundaries compared to surface scattering, and the impact of grain sizes and impurities will be discussed in detail.

Electrical assessment of copper damascene interconnects down to sub-50 nm feature sizes

The feasibility of fabrication of sub-50 nm copper interconnects was demonstrated. A process flow to obtain wires with line widths far below the limits given by lithography using a removable spacer technique was developed for copper damascene lines. The behavior of the electrical resistivity of lines with feature sizes down to 43 nm was investigated for temperatures ranging from 80 to 573 K. An increase of the electrical resistivity with shrinking dimensions was observed as a result of size effects. The experimental data will be discussed in detail and can be well described by a contribution of electron surface scattering and grain-boundary scattering. The results clearly demonstrate that cooling of Cu wires will no longer help to maintain low electrical resistivity in the mesoscopic regime, i.e. when feature sizes of metal wires approach the mean free path of the charge carriers. For future technology generations size effects, which are not explicitly addressed in the ITRS, will come into play and will become a significant contributor to wire related delay times.

Electrical characterization of copper interconnects with end-of-roadmap feature sizes

Abstract The metallization of trenches with end-of-roadmap feature sizes using a damascene approach is demonstrated. By applying an adapted spacer technique, narrow trenches were fabricated in an oxide-based intermetal dielectric, filled with barrier metal and Cu and subsequent CMP of the copper/barrier bi-layer. Thus damascene metal lines with widths down to 40 nm and aspect ratios exceeding 4 could be fabricated. These metal lines could be characterized electrically up to a length of almost 10 cm. The data show an increase of resistivity for small line widths, which can be explained by surface scattering. The surface effects can also be seen in the temperature dependence of the resistance. The maximum current density was shown to exceed those of todays interconnect lines by a factor of 2, exceeding the ITRS requirements for the maximum current density of such structures.

Damascene and subtractive processing of narrow tungsten lines: Resistivity and size effect

Narrow W lines with linewidths down to ~40 nm were manufactured by both damascene and subtractive processing. The dependence of the resistivity on the linewidth was studied for different deposition temperatures of the W layer. Generally, the resistivity decreases for decreasing deposition temperature of W. The resistivity increases with decreasing linewidth for both processes due to size effects. However, the W damascene lines show a much steeper increase of the resistivity than etched W lines. In the case of the etched lines the grain size is already fixed after deposition of the W and, therefore, the resistivity increase is caused by an increase of the surface scattering contribution solely. In the case of the damascene lines the line geometry restricts the grain size and, therefore, with decreasing linewidth both an increase of the grain boundary scattering and of the surface scattering contributes to the resistivity. The different behavior of the resistivities can be understood within a compact model ...

Processing technology for the investigation of sub-50 nm copper damascene interconnects

Abstract The scalability of today’s metallization in interconnect technology is demonstrated and nano-interconnects of critical dimension regarding the International Technology Roadmap for Semiconductors (ITRS) roadmap requirements for the 22 nm technology node are shown. Sub-50 nm copper damascene lines were fabricated using an adapted spacer technique with current optical lithography and standard manufacturing equipment for processing 150 or 200 mm diameter wafers. For comparison an electron beam microscope based lithography was used for direct writing of patterns with narrow pitches. For both methods particular attention will be paid to issues of patterning and adaptation of unit processes as well as metal deposition. Electrical measurements for assessing the fabricated nano-interconnects with respect to the influences of barrier and seed layer thicknesses are shown briefly. The feasibility of interconnects with end-of-roadmap feature sizes demonstrated by these measurements gives reason to expect a bright future of copper interconnect processing technology.

Secondary effects of single crystalline silicon deep-trench etching in a chlorine-containing plasma of 3-dimensional capacitor cells

Abstract The main problems occurring during the trench etching in a chlorine containing RIE process are considered: (1) deposition of contaminating films on the trench sidewalls, (2) micro masking effects of those contaminations leading to the so called “black silicom”, and (3) “trenching effects” on the bottom of the trench cell. By means of SIMS and Auger measurements it is shown that the contaminating films on the trench walls are formed by unsaturated B x Cl y species from the BCl 3 plasma. By the same analytical methods it is obtained that the so called black silicon occurring in a pure Cl 2 plasma is caused by micro masking by Al-, Si- oxide clusters which stem from surface adsorbed oxygen and the alumina covered cathode. Furthermore it is observed that the trenching effect occurring with Cl 2 plasma can be significantly reduced by adding BCl 3 . BCl 3 reduces the number of Cl + 2 ions and therefore favours the formation of passivating species on the surface to be etched. This passivating layer in return reduces the trench formation at the bottom.

A novel low-temperature (Ba,Sr)TiO 3 (BST) process with Ti/TiN barrier for Gbit DRAM applications

Abstract A new, low temperature (Ba,Sr)TiO 3 (BST) MOCVD process has been established at 580°C deposition temperature which can be used for Gbit DRAM applications using Ti TiN as barrier material. The process window for BST deposition was investigated in terms of deposition temperature, stoichiometry, film thickness, post annealing treatment and variation of the underlying electrode/barrier layer. Electrical characterization revealed specific capacitance values of 45 fF/μm 2 for 25 –30 nm film thickness and 75 fF/μm 2 for 10 nm film thickness which is close to the target value for GBit of 80 – 100 fF/μm 2 . Oxidation resistance of the Ti TiN barrier could be shown up to 600°C. Feasibility of this low temperature BST process has been successfully demonstrated using a 4 Mbit test vehicle.

Scaling of parasitics and delay times in the backend-of-line

The role of interconnects in determining the delay times of future generation integrated circuits has been studied. Two scenarios were investigated; one using ITRS values for dielectric permeability and conductor resistivity, and an alternative taking into account size effects on the resistivity and using more conservative values for k. To develop a concise model of the delays, the contributions of the individual parasitic elements and their evolution for future generations were investigated for the different scenarios. The calculations of the delays show a dramatic increase for small feature sizes. The predictions of the two models differ significantly especially for long wires, with the conservative model showing much longer delay times. These results make the introduction of a hierarchical metallization seem even more important.

Copper damascene interconnects for the 65 nm technology node: a first look at the reliability properties

Copper interconnects with end-of-roadmap feature sizes, fabricated in damascene technology, were electrically and thermally stressed to assess reliability performance. The maximum current carrying capability of 63 nm wide copper wires was found to be a factor of 2 higher when compared with current technologies. The impact of the Cu seed layer thickness on activation energy and stress voiding is discussed. The first lifetime estimations, assuming the ITRS roadmap requirements, were also made.

Challenges of interconnection technology till the end of the roadmap and beyond

Electrical results obtained with interconnects with end-of-roadmap feature sizes give confidence in a smooth and evolutionary extension of local interconnect technology for at least one decade. The requirements regarding RC signal delay for intermediate and global interconnects will not be met by technology alone like introduction of advanced low-k approaches such as airgaps, but will require further advances in disciplines which have not been product drivers in the past. Further advances in architecture, system design, and CAD tools will be indispensible and will become enablers for fabrication of CMOS products with CDs down to at least a few 10 nm. Further miniaturization driven by the need to reduce fabrication costs will result in further performance gain from device scaling without compromizing performance by interconnect signal delay. An interconnect crisis is avoidable.