Eugen Unger

Carbon nanotubes in interconnect applications

Carbon nanotubes with their outstanding electrical and mechanical properties are suggested as an interconnect material of the future. In this paper we will introduce nanotubes, compare their electrical properties with equivalent metal wires made of gold and describe our progress in process integration. Multi-walled carbon nanotubes are grown on 6-inch wafers in a batch process. The resulting nanotubes are evaluated with respect to their conductance as single multiwalled nanotubes and in their implementation as interconnects in vias and contact holes.

Carbon nanotubes for interconnect applications

We briefly review the status of the application of carbon nanotubes (CNTs) for future interconnects and present results concerning possible integration schemes. Growth of single nanotubes at lithographically defined locations (vias) has been achieved which is a prerequisite for the use of CNTs as future interconnects. For the 20 nm node a current density of 5/spl middot/10/sup 8/ A/cm/sup 2/ and a resistance of 7.8 k/spl Omega/ could be achieved for a single multi-walled CNT vertical interconnect.

Sub-20 nm short channel carbon nanotube transistors.

Carbon nanotube field-effect transistors with sub-20 nm long channels and on/off current ratios of >10(6) are demonstrated. Individual single-walled carbon nanotubes with diameters ranging from 0.7 to 1.1 nm grown from structured catalytic islands using chemical vapor deposition at 700 degrees C form the channels. Electron beam lithography and a combination of HSQ, calix[6]arene, and PMMA e-beam resists were used to structure the short channels and source and drain regions. The nanotube transistors display on-currents in excess of 15 microA for drain-source biases of only 0.4 V.

Electrochemical functionalization of multi-walled carbon nanotubes for solvation and purification

Abstract The chemical modification of multi-walled carbon nanotubes using electrolysis is described. It is found that the evolution of the halogens chlorine or bromine on an anode made from a foil of carbon nanotubes couples halogen atoms to the nanotube lattice. Furthermore, oxygen bearing functional groups, such as hydroxyl and carboxyl groups, are formed at the same time aiding solvation of the nanotubes in water or alcohol without any surfactant. Impurities and low grade modified nanotubes remain insoluble. The halogenated carbon nanotubes can be converted with sodium amide or triphenylmethyllithium to add the corresponding functional groups.

Bias dependence and electrical breakdown of small diameter single-walled carbon nanotubes

The electronic breakdown and the bias dependence of the conductance have been investigated for a large number of catalytic chemical vapor deposition grown single-walled carbon nanotubes (SWCNTs) with very small diameters. The convenient fabrication of thousands of properly contacted SWCNTs was possible by growth on electrode structures and subsequent electroless palladium deposition. Almost all of the measured SWCNTs showed at least weak gate dependence at room temperature. Large differences in the conductance and breakdown behavior have been found for “normal” semiconducting SWCNTs and small band-gap semiconducting SWCNTs.

Silicon nanowires: catalytic growth and electrical characterization

Nominally undoped silicon nanowires (NW) were grown by catalytic chemical vapor deposition. The growth process was optimized to control the NWs diameters by using different Au catalyst thicknesses on amorphous SiO 2 , Si 3 N 4 , or crystalline-Si substrates. For SiO 2 substrates an Ar plasma treatment was used to homogenize the catalyst coalescence, and thus the NWs diameter. Furthermore, planar field effect transistors (FETs) were fabricated by implementing 13 to 30 nm thin nominally undoped Si-NWs as the active region. Various silicides were investigated as Schottky-barrier source and drain contacts for the active region. For CoSi, NiSi and PdSi contacts, the FETs transfer characteristics showed p-type behavior. A FET consisting of a single Si-NW with 20 nanometers diameter and 2.5 μm gate-length delivers as much as 0.15 μA on-current at 1 volt bias voltage and has an on/off current ratio of 10 7 . This is in contrast to recent reports of low conductance in undoped Si.

Nanoelectronics Based on Carbon Nanotubes: Technological Challenges and Recent Developments

Abstract The semiconductor industry is expecting extraordinary technological challenges, so the readiness to integrate exotic materials with superior properties into microelectronic chips is increasing and new concepts are attracting more interest. This paper reviews recent research developments aimed at the design of carbon nanotube (CNT)‐based vertical interconnects. We introduce our concept for the integration of CNTs into microelectronic chips that is based on a combination of conventional technology, advanced processing methods (lithography and deposition), and self‐aligned processes.

Large-scale integration of carbon nanotubes into silicon-based microelectronics

The integration of carbon nanotubes (CNTs) into conventional silicon-technology with potential applications as interconnects, transistors, memory-cells, and sensors is an promising goal. Theoretical and experimental results indicate that CNT-based devices can outperform conventional silicon microelectronics. Concepts for the creation of vertical interconnects and transistors made out of CNTs, which allow a large scale integration, are presented. A vital step for their realization is the synthesis of individual CNTs with controlled diameters at lithographically predefined locations. Employing catalyst mediated Chemical Vapor Deposition (CVD) isolated CNTs have been grown out of holes in silicon dioxide which have been created by optical lithography. This allows the precise placement of individual CNTs on silicon substrates. Furthermore, the diameter of each CNT adjusts to the hole size, which makes it possible to control this important property separately for individual CNTs. In combination with the vertical integration concept those findings constitute a milestone in the parallel manufacture of nanotube-based devices with scalable batch processes.

Tuning the Polarity of Si-Nanowire Transistors Without the Use of Doping

In this article, a novel method of creating p- and n-type Si-NWs FETs by employing undoped NWs as the active region, is presented. This method does not require doping, but takes advantage of the inherent NW geometry and simply relies on the electrostatic control of the bands near the source- and drain- (S/D) contacts.

Non-Linear Gate Length Dependence of On-Current in Si-Nanowire FETs

An extensive gate-length (LG) dependent electrical characterization of silicon nanowire (NW) field effect transistors (FET) is presented here. Catalytically-grown and nominally undoped Si-NWs were integrated as the active region of FETs, upon which fully silicided Schottky source and drain contacts were fabricated. The length of the active region was shortened by a desired value, through the lateral self-aligned formation of nickel silicide source- and drain-segments. All Si-NW FETs consisting of a single Si-NW with diameters between 10 and 30 nm display p-type behaviour and on/off-current ratios of up to 10 7. Devices with LGs below 1 mum and 21 nm NW-diameters all show the same on currents around 1 muA at 1 V drain-source biases. For LG > 1 mum the on-current decreases exponentially with increasing LG