Wolfgang Klatzer

A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13/spl mu/m CMOS

Time-domain randomization of the unit current-cell refresh period converts the tonal behavior of cyclic background calibration into noise. Together with nested calibration of all DAC-segments a low-frequency SFDR of 83.7dB is achieved. The chip is fabricated in a standard 0.13mum CMOS process. Clocked at 200MHz, it consumes 25mW from a 1.5V supply.

A 350MHz low-OSR /spl Delta//spl Sigma/ current-steering DAC with active termination in 0.13 /spl mu/m CMOS

A time-interleaved architecture overcomes the dynamic performance limitations of standard DWA switching. Clocked at 350MHz, the DAC with active output buffer achieves a linearity of 76dB for a signal swing of 1.536V and an effective resolution of 11.9b in a bandwidth of 29.16MHz. It is fabricated in a standard 0.13 /spl mu/m CMOS process and consumes 62mW from a 1.5V supply.

Nonlinear distortion in current-steering D/A-converters due to asymmetrical switching errors

Asymmetrical switching errors introduce even harmonic distortion products in the differential output signal of a current-steering NRZ D/A-converter. Dynamic element matching techniques, originally intended to shape the mismatch induced nonlinearity into wide-band noise, can even worsen the dynamic performance of such converters due to their increased switching activity. A simple mathematical model to formalize this effect is presented and verified with simulations.

A 1.5V 13bit 130-300MS/s self-calibrated DAC with active output stage and 50MHz signal bandwidth in 0.13μm CMOS

A high-performance 13 bit current-steering DAC for analog subsystems is implemented in a standard 0.13 mum CMOS technology. A novel dynamic background calibration scheme directly trims the unary DAC-elements in differently weighted segments of the current source array. Interleaved current cells implement an effective RZ- behavior with NRZ output current waveform, which improves the dynamic linearity of the converter by 20 dB at 64 MHz. Clocked at 130 MHz, the converter draws 53 mW from a 1.5 V supply and achieves a SFDR > 73 dB for signal frequencies up to Nyquist. Operated at 300 MS/s with a 3x interpolation filter, the converter consumes 73 mW and achieves a SFDR > 68dB within the signal bandwidth of 50 MHz.

Smart CMOS Current-Steering D/A-Converters for Embedded Applications

The current-steering D/A-converter is the workhorse for the synthesis of high-resolution, wide-bandwidth analog signals, e.g. in the transmitter section of digital transceivers. Highly integrated systems require the implementation of such circuits in a nanometer CMOS technology together with analog and digital signal processing functions. Multi-mode operation additionally complicates the design task, since it is desired to minimize the circuit overhead in terms of silicon area and power consumption. “Smart” data converters make use of auxiliary analog and digital circuitry to enhance the linearity and to eventually tailor the converter architecture to the specific operating mode.