Wolfgang Rosner

Short-channel vertical sidewall MOSFETs

Vertical MOSFETs have been proposed in the roadmap of semiconductors as a candidate for sub-100-nm CMOS technologies. In this paper, vertical n-channel MOSFETs with channel length down to 50 nm are presented, fabricated in a standard production line with i-line lithography. A process flow using side wall gates and implantations instead of multiple layer depositions reduces process complexity and offers better CMOS compatibility. With this particular vertical MOSFET structure, called the vertical sidewall MOSFET, high doping concentrations in the channel are needed for sub-100-nm devices. The uniform channel doping is more critical for vertical transistors than for a planar technology, where optimized profiles can be easier implemented. Therefore, we investigated vertical MOSFETs with high channel doping concentration up to 1/spl times/10/sup 19/ cm/sup -3/ and channel lengths down to 50 nm. The impact of the high doping levels on threshold voltage and on tunneling currents is discussed. Finally, by using slight process modifications first results on vertical double-gate MOSFETs will be presented, which in principle can operate with an undoped channel region.

Vertical MOS transistors with 70 nm channel length

Vertical nMOS transistors with channel lengths down to 70nm and thin gate oxides have been fabricated using LPCVD epitaxy for the definition of the channel region instead of fine line lithography. The devices show drain current and transconductance values comparable to very advanced planar transistors. For the shortest channel length a stronger increase of current is observed and is attributed to ballistic and floating substrate effects. Besides high saturation currents due to very short channel lengths a higher integration density seems to be feasible using this vertical transistor technology.

Simulation of single electron circuits

A Monte Carlo simulator has been developed for the investigation of arbitrary single electron circuits. After a brief discussion of the fundamental effect we sketch the procedure used in the program. As an application, two circuits are analyzed under various conditions, especially considering possible high temperature operation.

Short Channel Vertical Sidewall Transistors

For the first time vertical n-channel MOSFETs with implanted S/D-regions and channel lengths down to 50 nm are presented, fabricated in a standard production line with iline lithography. These 50 nm transistors exhibit an excellent transconductance of 560 μS/μm, but suffer from short channel effects in the subthreshold region. The devices with 100 nm channel length, having a somewhat reduced transconductance of 445 μS/μm, showed a very low off-current of 5 pA/μm. We thereby demonstrate the possibility of integrating a high performance short channel transistor in a conventional CMOS process.