Wook-ghee Hahn

A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology

The market growth of mobile applications such as smart phones and tablet computers has fueled the explosive demand of NAND Flash memories having high density and fast throughput. To meet such a demand, we present a 64Gb multilevel cell (MLC) NAND Flash memory having 533Mb/s DDR interface in sub-20nm technology. Large floating-gate (FG) coupling interference and program disturbance are major challenges to impede the scaling of NAND Flash memories in sub-20nm technology node [1]. In this paper, we present correction-before-coupling (CBC) reprogram and P3-pattern pre-pulse scheme, allowing us to overcome large FG coupling interferences. We improve program disturbance by inventing inhibit-channel-coupling-reduction (ICCR) technique. In addition, we achieve a 533Mb/s DDR interface by employing a wave-pipeline architecture [2].

A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate

Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as shorter tPROG, lower power consumption and higher endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance. However, the previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking technology has been developed. As a result of long and focused research in 3D stacking technology, we succeed in developing 128 Gb 3b/cell Vertical NAND with 32 stack WL layers for the first time, which is the smallest 128 Gb NAND Flash. The die size is 68.9 mm 2, program time is 700 us and I/O rate is 1 Gb/s.

7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate

Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as smaller tPROG, lower power consumption and longer endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance. However, the previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking technology has been developed. As a result of long and focused research in 3D stacking technology, 128Gb 2b/cell device with 24 stack WL layers was announced in 2014 [1].

DIBL-Induced Program Disturb Characteristics in 32-nm NAND Flash Memory Array

In this brief, we have investigated the program disturb characteristics caused by drain-induced barrier lowering (DIBL) in a 32-nm nand Flash memory device. It was found that the VTH shift of the (N + 2)th erased state cell is larger than that of the (N + 1)th erased state cell if it is assumed that the channel of the Nth cell is cut off. It is revealed that the cut off is caused by a cell-to-cell coupling effect that is becoming more severe in the development of high-density Flash memory arrays.

A Compact Model for Channel Coupling in Sub-30 nm NAND Flash Memory Device

This paper presents an analytic model for NAND flash array where channel coupling embodies. Channel coupling effect which is becoming a more serious issue in developing high-density flash memory devices should be effectively suppressed. By applying the coupling model to a 30-nm NAND flash product, the simulation showed a good agreement with the measurement results. Also, complex problems in scaled NAND flash memories could be accurately explained by circuit simulations. This evaluation will be useful in developing high-density multi-level cell (MLC) NAND flash technologies.

A new GIDL phenomenon by field effect of neighboring cell transistors and its control solutions in sub-30 nm NAND flash devices

We present a new field effect mechanism on IGIDL in NAND flash strings. According to the proposed 5-terminal GIDL model, special care should be taken to optimize the biasing levels of inhibit scheme. Suggested incremental biasing scheme can be one of the solutions for reducing critical field that enhances boosting efficiency and maximizes memory yields.

Accurate Compact Modeling for Sub-20-nm nand Flash Cell Array Simulation Using the PSP Model

In this paper, we have developed a new floating-gate-type Flash cell compact model based on the channel potential by using PSP metal-oxide-semiconductor description. Cell-to-cell coupling, Fowler-Nordheim tunneling, and new leakage current formulas have been implemented on Verilog-A compact model. The channel potential calculation of the PSP model enables accurate modeling of channel coupling and leakage currents which are associated with the boosted channel. In addition, the model parameter extraction procedure through 3-D technology computer-aided design (TCAD) and SPICE simulation is presented. The simulation results agree well with measured data of sub-20-nm nand cells.

A Simple compact model for hot carrier injection phenomenon in 32 nm NAND flash memory device

In this work, a SPICE-friendly hot carrier injection (HCI) model for NAND flash memory has been proposed. By applying the HCI model to the 32 nm NAND product, the simulation based on HCI model showed good agreement with the measurement results. Based on the proposed model, a complex problem regarding the program disturbance in the scaled NAND flash memory array can be predicted through simple circuit simulations. Moreover, it is very useful in developing the ultra-short channel devices for high density multi-level cell (MLC) NAND flash technologies.