Woonyun Kim

A Linear Multi-Mode CMOS Power Amplifier With Discrete Resizing and Concurrent Power Combining Structure

Efficiency degradation effects of power combining transformers with partially disabled inputs are quantitatively analyzed. To improve efficiencies in lower-power modes of a multi-mode class-AB power amplifier (PA), a discrete resizing technique is introduced in combination with a parallel-combining transformer (PCT). The two-stage PA implemented in a 0.18-μm CMOS technology also includes varactor-based tunable matching circuits. The design method involves parallel-combining of two power stages, each of which are divided into three sub-cells to facilitate discrete resizing. The parallel-combining of concurrently resized power cells minimizes undesired power loss through the transformer and helps the PA to utilize the transformer efficiency maximally independent of the number of combining cells. When operating in the high-power mode, the PA exhibits a peak output power of 31 dBm with a PAE of 34.8%. Power back-offs are realized by discretely turning off parallel sub-amplifier cells concurrently, achieving output power levels of 26 dBm and 22.3 dBm with respective PAE of 22.5% and 15%. The EVM has been measured with IEEE 802.11g WLAN and 802.16e WiMAX modulated signals in three operation modes. In the high-power mode, the PA dissipates 590 mA from a 3.3 V supply.

A 3.6mW differential common-gate CMOS LNA with positive-negative feedback

A common-gate (CG) LNA has been widely investigated because it features superior bandwidth, linearity, stability, and robustness to PVT variations compared to a common-source (CS) topology [1]. In spite of these advantages, the dependence of gain and NF on the restricted transconductance (gm) renders this topology unsuitable for various wireless applications. The input impedance of a CG LNA is simplified as 1/gm, and the noise factor is inversely proportional to gm [2]. In order to achieve high gain and low NF, gm should be increased, which deteriorates the 50Ω input impedance matching for a conventional CG LNA.

A 2.4 GHz Fully Integrated Linear CMOS Power Amplifier With Discrete Power Control

A fully integrated 2.4 GHz CMOS power amplifier (PA) in a standard 0.18 mum CMOS process is presented. Using a parallel-combining transformer (PCT) and gate bias adaptation, a discrete power control of the PA is achieved for enhancing the efficiency at power back-off. With a 3.3 V power supply, the PA has a peak drain efficiency of 33% at 31 dBm peak output power. By applying discrete power control, a reduction of 650 mA in current consumption can be achieved over the low output power range while satisfying the EVM requirements of WLAN 802.11g and WiMAX 802.16e signals.

Intermodulation mechanism and linearization of AlGaAs/GaAs HBTs

The intermodulation (IM) mechanism of heterojunction bipolar transistors (HBTs) has been studied by using an analytical nonlinear equivalent circuit model and Volterra-series analysis of the model. Although the third-order IM intercept point (IP3) does not depend on the emitter parameter, it is appreciably affected by base and collector parameters and has been substantially improved by utilizing punchthrough collector structure. The measured IP3 of punchthrough collector HBTs is 31 dBm with 150-mW dc power, which is higher than that of normal collector HBTs by 3 dB. The investigation of the cancellation effects of nonlinear elements reveals that the output nonlinear current components generated by emitter-base current source and base-collector current source cancel each other almost exactly, resulting in high linear characteristics of HBTs.

A Fully-Integrated High-Power Linear CMOS Power Amplifier With a Parallel-Series Combining Transformer

In this paper, a linear CMOS power amplifier (PA) with high output power (34-dBm saturated output power) for high data-rate mobile applications is introduced. The PA incorporates a parallel combination of four differential PA cores to generate high output power with good efficiency and linearity. To implement an efficient on-chip power combiner in a small form-factor, we propose a parallel-series combining transformer (PSCT), which mitigates drawbacks and limitations of conventional power-combining transformers such as a series combining transformer (SCT) and a parallel combining transformer (PCT). Using the proposed PSCT, a two-stage class-AB PA is designed and fabricated in a 0.18-μm CMOS technology. The PA achieves a P1dB of 31.5 dBm , a Psat of 34 dBm, and a Plinear of 23.5 dBm with a peak PAE of 34.9% (peak drain efficiency of 41%) at the operating frequency of 2.4 GHz . A detailed analysis of the proposed PSCT is introduced along with comparisons to the conventional monolithic power-combining transformers. A design methodology of the integrated CMOS PA is also presented.

A Wideband Low-Power CMOS LNA With Positive–Negative Feedback for Noise, Gain, and Linearity Optimization

A wideband common-gate (CG) low-noise amplifier (LNA) utilizing positive-negative-feedback technique is presented. The positive-negative-feedback technique boosts effective transconductance (Gm) and output impedance, which leads to an LNA with higher gain and lower noise figure (NF) over the previously reported amplifiers. In addition, this approach provides high linearity with an aid of third harmonic cancellation, and it breaks transconductance (gm) constriction for input matching in CG amplifiers. In this paper, linearity and output impedance improvement through the proposed technique are fully analyzed. An LNA prototype is implemented in 0.18- μm CMOS technology occupying a total area of 0.33 mm2. The implemented LNA delivers a maximum voltage gain of 21 dB, a minimum NF of 2 dB, an third-order intermodulation intercept point of -3.2 dBm, and 3.6 mW of power consumption in 300-920 MHz of 3-dB bandwidth with input matching (S11 <; -10 dB).

A Low Power and Wide Range Programmable Clock Generator With a High Multiplication Factor

A programmable delay locked loop (DLL) based clock generator, providing a high multiplication factor, has been developed in a 0.18- μm CMOS technology. Utilizing the proposed pulse generator, purely consisting of D flip flops (DFFs) and inverters, the clock generator provides a high multiplication factor of up to 24. It consumes only 16.2 mW when generating 2.16 GHz output signals. In addition, the proposed saturated-type unit delay cell adopted in the voltage controlled delay line (VCDL) is capable of providing a long delay while maintaining fast-switching signal edges. Thus, the DLL can lock up an input reference frequency as low as 30 MHz while maintaining good phase noise performance and small chip area occupancy. The phase noise is -88.7 and -99.8 dBc/Hz at 10 kHz and 100 kHz offsets, respectively, from the operating frequency of 1.2 GHz, which is equivalent to a 1.7 ps RMS jitter. The active chip area takes only 0.051 mm2.

Spurious noise reduction by modulating switching frequency in DC-to-DC converter for RF power amplifier

The presence of a spectrum spreading effect in a DC-to-DC converter operating in Pulse-Width Modulation (PWM) with a modulated switching frequency is analyzed. A step-down DC-to-DC converter prototype with a digital PWM ramp signal modulator is implemented in a standard CMOS 0.18-µm process. The step-down DC-to-DC converter has an 6-bit up/down binary counter to vary its switching frequency between 2.2 MHz and 4.4 MHz in 64 steps as means of decreasing spurious noise peaks at the output of the switch converter. The measurement results show that the spurious switch noise peak is reduced by 12 dB when a monotonic frequency stepping with the up/down counter is used, and it is shown that the additional switching frequency modulation functionality does not degrade the overall efficiency and the closed loop operation significantly.

A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump PLL

This paper proposes a new reference-spur elimination architecture for a charge-pump-based phase locked loop (PLL) using an edge interpolation technique. By utilizing a charge-distribution mechanism on the control voltage of the voltage-controlled oscillator, the proposed architecture is capable of suppressing high-order harmonics of the reference spur, as well as a fundamental spur. In implementation, the eight-stage edge interpolator achieved more than 16-dB additional spur suppression. In addition, the harmonics of the reference spur within a 104-MHz frequency offset, the location of the eighth harmonic of the reference spur, were dramatically suppressed. The prototype PLL was fully integrated in a 0.18-μm CMOS technology, which occupies a 670 μm × 640 μm active chip area. Additional circuits for the edge interpolator consumes less than one-fifth of the total area and power.

A Low Phase Noise

A low phase noise and low power LC voltage-controlled oscillator (VCO) has been designed using a 65-nm CMOS process. The phase noise is minimized by switching the differential core using a rectangular shaped voltage waveform, which is formed by a harmonic tuned LC tank assisted by a gm3 boosting circuit. The gm3 boosting circuit effectively maximizes the slope at the zero crossing point and reduces the transition time in which the switching transistor is operated at the triode region. The rectangular switching technique has improved the phase noise of the oscillator by 10 dB. The 450 mum times 540 mum chip consumes 4.34 mW. The proposed VCO has phase noises of -83.3, -110.7, and -131.8 dBc/Hz at 10 KHz, 100 KHz, and 1 MHz offset frequencies, respectively, from the 1.6-GHz carrier frequency.