Woung-Moo Lee

A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using a NAND flash memory technology

A 3.3-V 16-Mb nonvolatile memory having operation virtually identical to DRAM with package pin compatibility has been developed. Read and write operations are fully DRAM compatible except for a longer RAS precharge time after write. Fast random access time of 63 ns with the NAND flash memory cell is achieved by using a hierarchical row decoder scheme and a unique folded bit-line architecture which also allows bit-by-bit program verify and inhibit operation. Fast page mode with a column address access time of 21 ns is achieved by sensing and latching 4 k cells simultaneously. To allow byte alterability, nonvolatile restore operation with self-contained erase is developed. Self-contained erase is word-line based, and increased cell disturb due to the word-line based erase is relaxed by adding a boosted bit-line scheme to a conventional self-boosting technique. The device is fabricated in a 0.5-/spl mu/m triple-well, p-substrate CMOS process using two-metal and three-poly interconnect layers. A resulting die size is 86.6 mm/sup 2/, and the effective cell size including the overhead of string select transistors is 2.0 /spl mu/m/sup 2/.

A novel NAND structure with a BJT contact for the high density mask ROMs

A novel NAND cell structure with a PNP BJT, which amplifies the cell current, was proposed and fabricated. Its typical current gain is around 10 and the measured cell current is about 180 /spl mu/A at 25/spl deg/C. This amount is extremely high compared to that of the conventional NAND cell structure. This structure also keeps good current driving capability regardless of temperature variation while full MOS type degrades the characteristics. This results indicate that this new structure is a strong candidate for high performance and high density mask ROMs.<<ETX>>

A 3.3 V 16 Mb nonvolatile virtual DRAM using a NAND flash memory technology

A 3.3V 16Mb nonvolatile memory has read and write operations fully DRAM-compatible except a longer RAS precharge time after write. Most systems with high-performance processors use a shadow nonvolatile memory uploaded to a fast DRAM to obtain zero wait-state performance. The introduced nonvolatile virtual DRAM (NVDRAM) eliminates the need for this redundancy, achieving high performance while reducing power consumption. Fast random access time (tRAC) with a NAND flash memory cell is achieved by using a folded bit-line architecture, and DRAM comparable column address access time (tkA) is achieved by sensing and latching 4k cells simultaneously.